The invention relates to a memory device and the like. The memory device comprises one or more memory block. The memory block has a memory cell array consists of multiple memory cells (210) arranged in a matrix form. A region of the multiple memory cells (210) includes multiple divisional domains (201a-201e) divided in the direction along word line (WL). Each of the word lines (WL) has multiple divisional selection lines (WLa-WLe) divided corresponding to the multiple divisional domains. The memory block has a switching mechanism (220) for switching the divisional word lines (Wt) that are to be simultaneously activated in each of the divisional domains. Multiple memory cells (210) associated with each of the divisional word lines store a horizontal or vertical array of pixel data. The inventive memory device enables simultaneous access to multiple items of pixel data constituting a pixel block having an arbitrary configuration.