Invention Application
US20090168942A1 Apparatus and method for frequency synthesis using delay locked loop
有权
使用延迟锁定环路进行频率合成的装置和方法
- Patent Title: Apparatus and method for frequency synthesis using delay locked loop
- Patent Title (中): 使用延迟锁定环路进行频率合成的装置和方法
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Application No.: US12317527Application Date: 2008-12-23
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Publication No.: US20090168942A1Publication Date: 2009-07-02
- Inventor: Yun-Young Choi , Hoon-Tae Kim
- Applicant: Yun-Young Choi , Hoon-Tae Kim
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Priority: KR10-2007-0137377 20071226
- Main IPC: H03D3/24
- IPC: H03D3/24 ; H03L7/06

Abstract:
An apparatus and method for frequency synthesis using a Delay Locked Loop (DLL) are provided. The apparatus includes the DLL, an edge pulse generator, and an inductive-capacitive (LC) tank switch. If phases of a reference frequency signal and a feedback signal are the same and thus are locked, the DLL delays the reference frequency signal. The edge pulse generator generates a plurality of pulse signals representing phase delay amounts of signals. The LC tank switch combines the plurality of pulse signals and generates frequency.
Public/Granted literature
- US08259889B2 Apparatus and method for frequency synthesis using delay locked loop Public/Granted day:2012-09-04
Information query
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