发明申请
US20090174431A1 METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE 失效
通用程序控制总线架构的方法和装置

  • 专利标题: METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE
  • 专利标题(中): 通用程序控制总线架构的方法和装置
  • 申请号: US12401055
    申请日: 2009-03-10
  • 公开(公告)号: US20090174431A1
    公开(公告)日: 2009-07-09
  • 发明人: Peter M. PaniBenjamin S. Ting
  • 申请人: Peter M. PaniBenjamin S. Ting
  • 主分类号: H03K19/177
  • IPC分类号: H03K19/177
METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE
摘要:
An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.
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