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    Architecture and interconnect scheme for programmable logic circuits
    6.
    发明授权
    Architecture and interconnect scheme for programmable logic circuits 失效
    可编程逻辑电路的架构和互连方案

    公开(公告)号：US07646218B2

    公开(公告)日：2010-01-12

    申请号：US12215118

    申请日：2008-06-24

    申请人： Benjamin S. Ting

    发明人： Benjamin S. Ting

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

    摘要： An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer of routing network lines provides connectability between different first layers of routing network lines. Additional layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as the prior cell count in the array increases while the length of the routing lines and the number of routing lines also increases. Switching networks are used to provide connectability among same and different layers of routing network lines, each switching network composed primarily of program controlled passgates and, when needed, drivers.

    摘要翻译： 用于现场可编程门阵列（FPGA）的分层互连方案架构。 第一层路由网络线路用于提供块连接器组之间的连接，其中块连接器用于提供逻辑单元之间的连接性和对分层路由网络的可访问性。 第二层路由网络线路提供不同第一层路由网络线路之间的连接性。 路由网络线路的附加层被实现以提供不同的现有路由网络线路之间的可连接性。 当阵列中的先前单元计数增加时，单元数量增加，而路由线路长度和路由线路数量也增加时，将添加一个额外的路由层。 交换网络用于在相同和不同层次的路由网络线路之间提供可连接性，每个交换网络主要由程序控制的门户组成，并且在需要时由驱动程序组成。

    Scalable non-blocking switching network for programmable logic
    7.
    发明授权
    Scalable non-blocking switching network for programmable logic 有权
    可编程逻辑的可扩展非阻塞交换网络

    公开(公告)号：US07557613B2

    公开(公告)日：2009-07-07

    申请号：US12174080

    申请日：2008-07-16

    申请人： Peter M. Pani ,  Benjamin S. Ting

    发明人： Peter M. Pani ,  Benjamin S. Ting

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K17/002 ,  H04L49/15 ,  H04L49/1515 ,  Y10T29/49002 ,  Y10T29/49117

    摘要： A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.

    摘要翻译： 具有开关和中间（级）导体的可扩展的非阻塞交换网络（SN），其用于在相应的互连资源约束内以大致无限制的方式将第一多个导体连接到其它多组导体。 SN可以应用在广泛的应用中，一起或分层，以提供在网络，路由器和可编程逻辑电路中使用的大型交换机网络。 SN用于将第一组导体（通过SN）连接到给定逻辑电路层级中的多组导体，由此多个组中的每一个中的导体是等同的或可交换的，其在结构上使得 当用于下一级电路层级时，第一组导体相当。 SN可针对大型导体组进行扩展，可以分级使用，以实现大尺寸电路之间的可编程互连。

    Scalable non-blocking switching network for programmable logic
    8.
    发明授权
    Scalable non-blocking switching network for programmable logic 有权
    可编程逻辑的可扩展非阻塞交换网络

    公开(公告)号：US07256614B2

    公开(公告)日：2007-08-14

    申请号：US11218419

    申请日：2005-09-01

    申请人： Peter M. Pani ,  Benjamin S. Ting

    发明人： Peter M. Pani ,  Benjamin S. Ting

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K17/002 ,  H04L49/15 ,  H04L49/1515 ,  Y10T29/49002 ,  Y10T29/49117

    摘要： A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect substantially a first plurality of conductors, through a first set of switches, to a second plurality sets of conductors. The conductors in each set of the second plurality of conductors substantially connect, through a second set of switches, to a third plurality of sets of conductors. Each conductor of a set of the third plurality sets of conductors either connects, physically, to one pin in each of a plurality of functional blocks or, through a third set of switches, to a subsequent fourth plurality sets of conductors. The SN is scalable for large sized sets of conductors and can be used hierarchically in, for example, an integrated circuit or in an electronic system.

    摘要翻译： 具有开关和中间（级））导体的可扩展非阻塞交换网络（SN），其用于将基本上第一组多个导体通过第一组开关连接到第二多组导体。 第二组多个导体的每组中的导体通过第二组开关基本上连接到第三组多组导体。 一组第三组多个导体中的每个导体在物理上连接到多个功能块中的每一个中的一个引脚，或者通过第三组开关连接到随后的第四多组导体。 SN可用于大尺寸导体组，并且可以在例如集成电路或电子系统中分层使用。

    Method and apparatus for universal program controlled bus architecture
    9.
    发明授权
    Method and apparatus for universal program controlled bus architecture 有权
    通用程控总线架构的方法和装置

    公开(公告)号：US06781410B2

    公开(公告)日：2004-08-24

    申请号：US10412975

    申请日：2003-04-11

    申请人： Peter M. Pani ,  Benjamin S. Ting

    发明人： Peter M. Pani ,  Benjamin S. Ting

    IPC分类号： H03K19177

    CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/1778 ,  H03K19/17796

    摘要： The system and method of the present invention provides an innovative bus system of lines which can be programmed and to provide data, control and address information to the logic circuits interconnected by the bus system. This flexible structure and process enables a configurable system to be created to programmably connect one or more logic circuits, such as megacells. The programmability of the bus system enables the cascading of multiple megacells in an arbitrary fashion (i.e., wide, deep or both) and the sharing of common lines for system level communication.

    摘要翻译： 本发明的系统和方法提供了一种创新的线路总线系统，其可以被编程并且向由总线系统互连的逻辑电路提供数据，控制和地址信息。 这种灵活的结构和过程使得能够创建可配置系统以可编程地连接一个或多个逻辑电路，例如兆位。 总线系统的可编程性使得能够以任意方式（即，宽，深或两者）级联多个兆位，并且共享用于系统级通信的公共线。

    Architecture and interconnect scheme for programmable logic circuits
    10.
    发明授权
    Architecture and interconnect scheme for programmable logic circuits 失效
    可编程逻辑电路的架构和互连方案

    公开(公告)号：US06703861B2

    公开(公告)日：2004-03-09

    申请号：US10269364

    申请日：2002-10-11

    申请人： Benjamin S. Ting

    发明人： Benjamin S. Ting

    IPC分类号： H03K19177

    CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

    摘要： An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer. Other switching networks provide connectability between the routing network lines corresponding to the first layer to routing network lines corresponding to the second layer. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as a square function of two of the prior cell count in the array while the length of the routing lines and the number of routing lines increases as a linear function of two. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.

    摘要翻译： 用于现场可编程门阵列（FPGA）的架构和分布式分层互连方案。 FPGA由多个对输入信号执行逻辑功能的单元组成。 可编程的内连接将属于逻辑集群的小区的每个输出之间的连接性提供给属于该逻辑集群的每个其他小区的至少一个输入。 一组可编程块连接器用于提供单元的逻辑簇之间的可连接性以及对分层路由网络的可访问性。 使用均匀分布的第一层路由网络线路来提供块连接器组之间的连接。 实现均匀分布的第二层路由网络线路以提供不同第一层路由网络线路之间的可连接性。 交换网络用于提供块连接器与对应于第一层的路由网络线路之间的可连接性。 其他交换网络提供对应于第一层的路由网络线路与对应于第二层的路由网络线路之间的可连接性。 实现了额外的均匀分布的路由网络线路层以提供不同的现有路由网络线路之间的可连接性。 当单元的数量作为阵列中的两个先前单元计数的平方函数增加时，添加另外的路由层，而路由线的长度和路由线的数量增加为两个的线性函数。 可编程双向passgates用作开关，用于控制要连接的路由网络线路。