发明申请
US20090177457A1 DUTY CYCLE DISTORTION (DCD) JITTER MODELING, CALIBRATION AND GENERATION METHODS
有权
占空比失真（DCD）抖动建模，校准和生成方法
- 专利标题： DUTY CYCLE DISTORTION (DCD) JITTER MODELING, CALIBRATION AND GENERATION METHODS
- 专利标题（中）： 占空比失真（DCD）抖动建模，校准和生成方法
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申请号： US11968942申请日： 2008-01-03
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公开(公告)号： US20090177457A1公开(公告)日： 2009-07-09
- 发明人: Xingdong Dai , Weiwei Mao , Max J. Olsen , Geoffrey Zhang
- 申请人： Xingdong Dai , Weiwei Mao , Max J. Olsen , Geoffrey Zhang
- 申请人地址： US PA Allentown
- 专利权人： Agere Systems Inc.
- 当前专利权人： Agere Systems Inc.
- 当前专利权人地址： US PA Allentown
- 主分类号： G06G7/62
- IPC分类号： G06G7/62
摘要：
A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a filtering process of the clock DCD signal. Once the clock DCD signal is calibrated, a data DCD signal is generated and calibrated based upon results obtained from a filtering process of the data DCD signal.
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