公开(公告)号：US20140025350A1

公开(公告)日：2014-01-23

申请号：US13553983

申请日：2012-07-20

申请人： Xingdong Dai ,  Yasser Ahmed

发明人： Xingdong Dai ,  Yasser Ahmed

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Operations of an electronic device are simulated by generating and executing a bit-accurate model of the device using an input signal having at least one transition that corresponds to a step input having a pre-transition value (e.g., 0 for a positive transition) for a specified duration before the transition and a post-transition value (e.g., 1 for a positive transition) for a specified duration after the transition. The corresponding step-response results are differentiated with respect to time to generate impulse-response results for the device. The impulse-response results are converted into the frequency domain to determine frequency-domain characteristics of the device that are used to generate a statistical model of the device, which can be executed to simulate all operations of the device, include low bit-error-rate (BER) simulations that would take too long to simulate using the bit-accurate model.

摘要翻译： 通过使用具有至少一个转换的输入信号来生成和执行装置的比特精确模型来模拟电子装置的操作，所述转换对应于具有预转换值的步进输入（例如，对于正转换为0），用于 转换前的指定持续时间和过渡后的指定持续时间后的转换后值（例如，1为正转移）。 相应的步进响应结果相对于时间被区分以产生该装置的脉冲响应结果。 脉冲响应结果被转换为频域以确定用于生成设备的统计模型的设备的频域特性，其可以被执行以模拟设备的所有操作，包括低位误差 - 速率（BER）模拟，需要太长时间来模拟使用位精确模型。

公开(公告)号：US08559580B2

公开(公告)日：2013-10-15

申请号：US12494771

申请日：2009-06-30

申请人： Xingdong Dai ,  Dwight David Daugherty ,  Max J. Olsen ,  Lane A. Smith ,  Geoffrey Zhang

发明人： Xingdong Dai ,  Dwight David Daugherty ,  Max J. Olsen ,  Lane A. Smith ,  Geoffrey Zhang

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H04L1/20

摘要： Techniques are disclosed for asynchronous calibration for eye diagram generation. For example, a method for calibrating a process for generating a data eye associated with a received signal comprises the following steps. Samples of the received signal are obtained for a first unit interval using a first data latch and a roaming latch. A delay offset is determined between the first data latch and the roaming latch by comparing at least one sample obtained using the first data latch and at least one sample obtained using the roaming latch, wherein the delay offset determined by the comparison is used to calibrate the process for generating the data eye associated with the received signal. A similar comparison may be done for a second data latch and used to calibrate the process. The method is able to find the accurate position of each data latch with respect to the roaming latch so as to improve the accuracy of data decoding in a digital receiver, i.e., provide receiver optimization.

摘要翻译： 公开了用于眼图生成的异步校准的技术。 例如，用于校准与接收信号相关联的用于生成数据眼的处理的方法包括以下步骤。 使用第一数据锁存器和漫游锁存器，以第一单位间隔获得接收信号的样本。 通过比较使用第一数据锁存器获得的至少一个样本和使用漫游锁存器获得的至少一个样本，在第一数据锁存器和漫游锁存器之间确定延迟偏移，其中由比较确定的延迟偏移用于校准 用于产生与接收信号相关联的数据眼的过程。 可以对第二数据锁存器进行类似的比较，并用于校准该过程。 该方法能够找到每个数据锁存器相对于漫游锁存器的准确位置，以提高数字接收机中数据解码的准确度，即提供接收机优化。

公开(公告)号：US20130251007A1

公开(公告)日：2013-09-26

申请号：US13425467

申请日：2012-03-21

申请人： Yasser Ahmed ,  Xingdong Dai

发明人： Yasser Ahmed ,  Xingdong Dai

IPC分类号： H04B1/38

CPC分类号： H04L7/02 ,  H04L7/0337

摘要： In order to compensate for phase offset between different sets of circuitry having different synchronous clock domains, transmit (TX) circuitry of one domain is configured to transmit a pattern signal (e.g., a pseudo random bit sequence) to receive (RX) circuitry of the other domain. The RX circuitry cycles through a number of different phase-shifted RX clock signals to determine which selected clock signals result in valid RX pattern signals. The RX circuitry is then able to select one of the phase-shifted clock signals for use in normal processing of an RX data signal received from the TX circuitry.

摘要翻译： 为了补偿具有不同同步时钟域的不同电路组之间的相位偏移，一个域的发射（TX）电路被配置为发送模式信号（例如，伪随机位序列）以接收（RX）电路 其他域名 RX电路循环许多不同的相移RX时钟信号，以确定哪些选定的时钟信号产生有效的RX模式信号。 然后，RX电路能够选择一个相移时钟信号，以用于从TX电路接收的RX数据信号的正常处理。

公开(公告)号：US08428195B2

公开(公告)日：2013-04-23

申请号：US11967463

申请日：2007-12-31

申请人： Yasser Ahmed ,  Xingdong Dai ,  Mohammad S. Mobin ,  Lane A. Smith

发明人： Yasser Ahmed ,  Xingdong Dai ,  Mohammad S. Mobin ,  Lane A. Smith

IPC分类号： H04L27/06

CPC分类号： H04L27/01 ,  H04L7/0066 ,  H04L7/0083 ,  H04L25/4904

摘要： Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.

摘要翻译： 提供了用于检测和解码自适应均衡训练帧（具有包括二进制和二进制零序列的帧标记）的方法和装置。 通过移位接收到的数据来检测训练帧; 在移位的接收数据的一端插入至少一个二进制值以产生所接收数据的修改版本; 对所接收的数据应用逻辑功能以及当对应的位位置具有不同值时识别的接收数据的修改版本; 以及当所述逻辑功能的输出在第二二进制值的字符串的大致中间具有第一二进制值时，检测所述帧标记。 使用框架制造商的近似中心之间的距离和逻辑功能的输出中的预定二进制值对训练帧进行解码。

公开(公告)号：US20100027606A1

公开(公告)日：2010-02-04

申请号：US12221003

申请日：2008-07-30

申请人： Xingdong Dai ,  Geoffrey Zhang ,  Max Olsen ,  Dwight Daugherty

发明人： Xingdong Dai ,  Geoffrey Zhang ,  Max Olsen ,  Dwight Daugherty

IPC分类号： H03K5/159

CPC分类号： H04L25/03019

摘要： In described embodiments, an adaptive equalizer employed by a receiver in a communication channel, such as Fibre Channel, employs pattern recognition. When a repeating pattern, such as an IDLE or ARBFF pattern, is employed by a standard to, for example, maintain a communication link, an equalizer of the receiver might adaptively set its equalizer parameters based on characteristics of the signal energy of the repeating pattern rather than adaptively set its equalizer parameters based on characteristics of the signal energy of generally random user data carried on the link. Pattern recognition by the receiver allows for maintaining adaptive equalizer parameters at settings preferred for data detection of the typical random data, improving data detection performance of the receiver when the channel transitions from a preset or synchronization repeating pattern to a user random data pattern.

公开(公告)号：US20060192593A1

公开(公告)日：2006-08-31

申请号：US11068225

申请日：2005-02-28

申请人： Xingdong Dai

发明人： Xingdong Dai

IPC分类号： H03D13/00

CPC分类号： H03L7/095 ,  H04J3/0685

摘要： Methods and apparatus are provided for counter-based digital frequency lock detection. A counter-based digital frequency lock detector in accordance with the present invention comprises a reference counter clocked by a reference clock and a target counter clocked by a target clock. The target counter is n bits and n is less than a number of bits of the reference counter. A frequency offset violation of the target clock is detected by comparing a value of the target counter to an n bit counter.

摘要翻译： 提供了基于反数字频率锁定检测的方法和装置。 根据本发明的基于计数器的数字频率锁定检测器包括由参考时钟计时的参考计数器和由目标时钟计时的目标计数器。 目标计数器是n位，n小于参考计数器的位数。 通过将目标计数器的值与n位计数器进行比较来检测目标时钟的频偏偏移。

公开(公告)号：US06377086B1

公开(公告)日：2002-04-23

申请号：US09412491

申请日：1999-10-05

申请人： Laurence E. Bays ,  Dennis A. Brooks ,  Xingdong Dai ,  Richard Muscavage

发明人： Laurence E. Bays ,  Dennis A. Brooks ,  Xingdong Dai ,  Richard Muscavage

IPC分类号： H03B100

CPC分类号： H03K19/018521

摘要： A fully-static dual-voltage sense circuit designed for a mixed-voltage system senses the power-rail voltage of other devices that the device is interfaced with, and achieves a low-power consumption level without software assistance when the sensing circuit is active, and protects low-voltage process devices in the circuit from possible high voltage damage at the interface. In a preferred embodiment, the present invention includes an integrated circuit having a dual-voltage sense circuit, the sense circuit including a sense circuit input node supplied with an input voltage Vin; a sense circuit power input node supplied with a power-supply voltage; and a sense circuit output node outputting a digital signal of a voltage level equal to or less than the voltage level of a low-voltage digital signal, regardless of the voltage level of the input voltage.

摘要翻译： 设计用于混合电压系统的全静态双电压检测电路可以感测到器件接口的其他器件的电源电压，并且在感测电路处于活动状态时，无需软件辅助即可实现低功耗级别， 并保护电路中的低压工艺装置免受接口处的高压损坏。 在优选实施例中，本发明包括具有双电压检测电路的集成电路，感测电路包括提供有输入电压Vin的感测电路输入节点; 提供有电源电压的感测电路电力输入节点; 以及感测电路输出节点，输出等于或小于低电压数字信号的电压电平的电压电平的数字信号，而与输入电压的电压电平无关。

公开(公告)号：US08611406B2

公开(公告)日：2013-12-17

申请号：US12494805

申请日：2009-06-30

申请人： Xingdong Dai ,  Max J. Olsen ,  Scott A. Werner ,  Geoffrey Zhang

发明人： Xingdong Dai ,  Max J. Olsen ,  Scott A. Werner ,  Geoffrey Zhang

IPC分类号： H04B3/46 ,  H04B17/00 ,  H04Q1/20

CPC分类号： G01R31/3171

摘要： Communication system optimization using a soft receiver masking technique is disclosed. For example, a method for testing a communication device comprises obtaining a software representation of a receiver portion of a given communication device. A data signal received from a transmitter through a given link channel is then processed, wherein the processing step is performed using the software representation of the receiver portion of the communication device. An output signal is caused to be generated by the software representation of the receiver portion. An eye mask test is then applied to the output signal. Based on a result of the eye mask test, one or more parameters of the transmitter may be adjusted.

摘要翻译： 公开了使用软接收机屏蔽技术的通信系统优化。 例如，用于测试通信设备的方法包括获得给定通信设备的接收机部分的软件表示。 然后处理从发射机通过给定链路信道接收的数据信号，其中使用通信设备的接收机部分的软件表示来执行处理步骤。 由接收器部分的软件表示产生输出信号。 然后将眼罩测试应用于输出信号。 基于眼罩测试的结果，可以调整发射器的一个或多个参数。

公开(公告)号：US07882404B2

公开(公告)日：2011-02-01

申请号：US11935759

申请日：2007-11-06

申请人： Xingdong Dai ,  Geoffrey Zhang ,  Max J. Olsen

发明人： Xingdong Dai ,  Geoffrey Zhang ,  Max J. Olsen

IPC分类号： G01R31/28

CPC分类号： H04L25/03343 ,  H04L25/0264 ,  H04L25/0286 ,  H04L25/03057 ,  H04L25/4923

摘要： The present invention implements a method and apparatus for using components within a Serializer/DeSerializer (SerDes) to emulate the effects of a backplane in order to facilitate automated test equipment (ATE) testing of the SerDes. The SerDes includes a transmitter pre-emphasis circuit (TPXE) that pre-emphasizes a transmitted signal and a receiver equalization circuit (RXEQ) that equalizes a received signal. The TPXE includes coefficients that are dynamically programmable.

摘要翻译： 本发明实现了使用串行器/解串器（SerDes）内的组件来模拟背板的效果以方便SerDes的自动测试设备（ATE）测试的方法和装置。 SerDes包括预先强调发射信号的发射机预加重电路（TPXE）和均衡接收信号的接收机均衡电路（RXEQ）。 TPXE包括可动态编程的系数。

公开(公告)号：US07714667B2

公开(公告)日：2010-05-11

申请号：US11934426

申请日：2007-11-02

申请人： Xingdong Dai ,  Yasser Ahmed ,  Christopher J. Abel ,  Shawn Michael Logan

发明人： Xingdong Dai ,  Yasser Ahmed ,  Christopher J. Abel ,  Shawn Michael Logan

IPC分类号： H03L7/113

CPC分类号： H03L7/18 ,  H03L7/087 ,  H03L7/095 ,  H03L2207/06

摘要： The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.

摘要翻译： 本发明实现了一种用于校准锁相环（PLL）电路的装置。 该装置包括用于检测PLL电路中包含的参考信号和受控振荡器的频率的检测器。 检测器将频差输出到控制电路。 控制电路被编程为基于有序的频率差来调整一个或多个控制信号到受控振荡器以完成校准过程。