Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).