发明申请
- 专利标题: Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor
- 专利标题(中): 具有内部垂直互连结构的半导体芯片的半导体封装及其方法
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申请号: US12044803申请日: 2008-03-07
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公开(公告)号: US20090224402A1公开(公告)日: 2009-09-10
- 发明人: Byung Tai Do , Seng Guan Chow , Heap Hoe Kuan , Linda Pei Ee Chua , Rui Huang
- 申请人: Byung Tai Do , Seng Guan Chow , Heap Hoe Kuan , Linda Pei Ee Chua , Rui Huang
- 申请人地址: SG Singapore
- 专利权人: STATS CHIPPAC, LTD.
- 当前专利权人: STATS CHIPPAC, LTD.
- 当前专利权人地址: SG Singapore
- 主分类号: H01L23/488
- IPC分类号: H01L23/488 ; H01L21/60
摘要:
A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps.
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