发明申请
US20090235035A1 COMPUTER PROGRAM INSTRUCTION ARCHITECTURE, SYSTEM AND PROCESS USING PARTIAL ORDERING FOR ADAPTIVE RESPONSE TO MEMORY LATENCIES
审中-公开
计算机程序指导体系，系统和过程使用部分订购对存储器延迟的自适应响应
- 专利标题： COMPUTER PROGRAM INSTRUCTION ARCHITECTURE, SYSTEM AND PROCESS USING PARTIAL ORDERING FOR ADAPTIVE RESPONSE TO MEMORY LATENCIES
- 专利标题（中）： 计算机程序指导体系，系统和过程使用部分订购对存储器延迟的自适应响应
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申请号： US12404957申请日： 2009-03-16
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公开(公告)号： US20090235035A1公开(公告)日： 2009-09-17
- 发明人: David F. Bacon , Xiaowei Shen
- 申请人： David F. Bacon , Xiaowei Shen
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 主分类号： G06F12/00
- IPC分类号： G06F12/00
摘要：
The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend of ever-increasing processor speeds and attendant increases in memory latencies. These partial orders can be used to respond adaptively to memory latencies. It is shown how these constructs can be effectively supported with simple and inexpensive instruction set and micro-architectural extensions.
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