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1.发明申请COMPUTER PROGRAM INSTRUCTION ARCHITECTURE, SYSTEM AND PROCESS USING PARTIAL ORDERING FOR ADAPTIVE RESPONSE TO MEMORY LATENCIES 审中-公开计算机程序指导体系，系统和过程使用部分订购对存储器延迟的自适应响应公开(公告)号：US20090235035A1
公开(公告)日：2009-09-17
申请号：US12404957
申请日：2009-03-16
申请人： David F. Bacon , Xiaowei Shen
发明人： David F. Bacon , Xiaowei Shen
IPC分类号： G06F12/00
CPC分类号： G06F8/314 , G06F9/30076 , G06F9/30098
摘要： The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend of ever-increasing processor speeds and attendant increases in memory latencies. These partial orders can be used to respond adaptively to memory latencies. It is shown how these constructs can be effectively supported with simple and inexpensive instruction set and micro-architectural extensions.
摘要翻译： 本发明广泛地考虑了编织物和纤维，高级编程结构，其有助于创建部分排序的程序，以解决不断增长的处理器速度和伴随的存储器延迟增加的持续趋势。 这些部分顺序可用于自适应地响应内存延迟。 显示了如何通过简单和便宜的指令集和微架构扩展来有效地支持这些构造。
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公开(公告)号：US08799581B2
公开(公告)日：2014-08-05
申请号：US11620323
申请日：2007-01-05
CPC分类号： G06F12/0815 , G06F12/0817
摘要： Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize caches and avoid unnecessary cache thrashing and pollution. Hardware maintains color-based counters relative to the cache lines to monitor and obtain feedback on cache line events. These counters are utilized for cache coherence transactions in multiple processor systems.
摘要翻译： 基于颜色的缓存允许每个高速缓存行通过特定的颜色进行区分，并且可以基于高速缓存行的颜色来操作缓存行为。 当多个线程能够共享缓存时，有效的缓存管理对于整体性能至关重要。 基于色彩的缓存提供了一种有效的方法来更好地利用缓存，并避免不必要的缓存颠簸和污染。 硬件维护相对于高速缓存行的基于颜色的计数器，以监视和获取有关高速缓存行事件的反馈。 这些计数器用于多处理器系统中的高速缓存一致性事务。
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公开(公告)号：US20080168237A1
公开(公告)日：2008-07-10
申请号：US11620323
申请日：2007-01-05
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0817
摘要： Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize caches and avoid unnecessary cache thrashing and pollution. Hardware maintains color-based counters relative to the cache lines to monitor and obtain feedback on cache line events. These counters are utilized for cache coherence transactions in multiple processor systems.
摘要翻译： 基于颜色的缓存允许每个高速缓存行通过特定的颜色进行区分，并且可以基于高速缓存行的颜色来操作缓存行为。 当多个线程能够共享缓存时，有效的缓存管理对于整体性能至关重要。 基于色彩的缓存提供了一种有效的方法来更好地利用缓存，并避免不必要的缓存颠簸和污染。 硬件维护相对于高速缓存行的基于颜色的计数器，以监视和获取有关高速缓存行事件的反馈。 这些计数器用于多处理器系统中的高速缓存一致性事务。
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4.发明授权Systems and methods for indirect register access using status-checking and status-setting instructions 有权使用状态检查和状态设置指令进行间接注册访问的系统和方法公开(公告)号：US09003169B2
公开(公告)日：2015-04-07
申请号：US12404957
申请日：2009-03-16
申请人： David F. Bacon , Xiaowei Shen
发明人： David F. Bacon , Xiaowei Shen
CPC分类号： G06F8/314 , G06F9/30076 , G06F9/30098
摘要： The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend of ever-increasing processor speeds and attendant increases in memory latencies. These partial orders can be used to respond adaptively to memory latencies. It is shown how these constructs can be effectively supported with simple and inexpensive instruction set and micro-architectural extensions.
摘要翻译： 本发明广泛地考虑了编织物和纤维，高级编程结构，其有助于创建部分排序的程序，以解决不断增长的处理器速度和伴随的存储器延迟增加的持续趋势。 这些部分顺序可用于自适应地响应内存延迟。 显示了如何通过简单和便宜的指令集和微架构扩展来有效地支持这些构造。
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公开(公告)号：US07895392B2
公开(公告)日：2011-02-22
申请号：US11620348
申请日：2007-01-05
CPC分类号： G06F12/0842 , G06F12/121
摘要： Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize a cache and avoid unnecessary cache thrashing and/or pollution. The color based caching can be monitored to improve memory performance and guarantee Quality-Of-Service of cache utilization.
摘要翻译： 基于颜色的缓存允许每个高速缓存行通过特定的颜色进行区分，并且可以基于高速缓存行的颜色来操作缓存行为。 当多个线程能够共享缓存时，有效的缓存管理对于整体性能至关重要。 基于色彩的缓存提供了一种更好地利用缓存并避免不必要的缓存颠簸和/或污染的有效方法。 可以监控基于颜色的缓存，以提高内存性能，并保证高速缓存利用率的服务质量。
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6.发明授权Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies 失效计算机程序指令体系结构，系统和过程使用部分排序来适应对内存延迟的响应公开(公告)号：US07516306B2
公开(公告)日：2009-04-07
申请号：US10959609
申请日：2004-10-05
申请人： David F. Bacon , Xiaowei Shen
发明人： David F. Bacon , Xiaowei Shen
IPC分类号： G06F9/312
CPC分类号： G06F8/314 , G06F9/30076 , G06F9/30098
摘要： The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend of ever-increasing processor speeds and attendant increases in memory latencies. These partial orders can be used to respond adaptively to memory latencies. It is shown how these constructs can be effectively supported with simple and inexpensive instruction set and micro-architectural extensions.
摘要翻译： 本发明广泛地考虑了编织物和纤维，高级编程结构，其有助于创建部分排序的程序，以解决不断增长的处理器速度和伴随的存储器延迟增加的持续趋势。 这些部分顺序可用于自适应地响应内存延迟。 显示了如何通过简单和便宜的指令集和微架构扩展来有效地支持这些构造。
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公开(公告)号：US20080168230A1
公开(公告)日：2008-07-10
申请号：US11620348
申请日：2007-01-05
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F12/121
摘要： Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize a cache and avoid unnecessary cache thrashing and/or pollution. The color based caching can be monitored to improve memory performance and guarantee Quality-Of-Service of cache utilization.
摘要翻译： 基于颜色的缓存允许每个高速缓存行通过特定的颜色进行区分，并且可以基于高速缓存行的颜色来操作缓存行为。 当多个线程能够共享缓存时，有效的缓存管理对于整体性能至关重要。 基于色彩的缓存提供了一种更好地利用缓存并避免不必要的缓存颠簸和/或污染的有效方法。 可以监控基于颜色的缓存，以提高内存性能，并保证缓存利用率的服务质量。
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8.发明授权Adaptive mechanisms and methods for supplying volatile data copies in multiprocessor systems 有权用于在多处理器系统中提供易失性数据副本的自适应机制和方法公开(公告)号：US08131938B2
公开(公告)日：2012-03-06
申请号：US12248209
申请日：2008-10-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0831 , G06F2212/1016 , G06F2212/507
摘要： In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.
摘要翻译： 在具有存储器层次结构的计算机系统中，当高级缓存将数据拷贝提供给低级缓存时，共享副本可以是易失性的或非易失性的。 当数据拷贝稍后从低级缓存中替换时，如果数据拷贝是非易失性的，则需要将其写回高级缓存; 否则可以从低级缓存中简单地刷新。 高级缓存可以采用易失性预测机制，其自动地确定当高级缓存需要向低级缓存发送数据时是否应提供易失性拷贝或非易失性拷贝。 示例性的易失性预测机制建议如果高速缓存行已被低级缓存连续访问，则使用非易失性拷贝。 此外，低级缓存可以使用根据某些促销策略自动地将数据拷贝从易失性地改变为非易失性的易失性促进机制，或者根据某种降级策略将数据拷贝从非易失性变为不稳定。
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9.发明申请公开(公告)号：US20110107032A1
公开(公告)日：2011-05-05
申请号：US12985726
申请日：2011-01-06
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.
摘要翻译： 提供了一种重新配置高速缓冲存储器的方法。 一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征，并且基于所分析的一个或多个特征重新配置高速缓存。 分析特性的示例可以包括但不限于执行实体使用的数据结构，执行实体的预期参考模式，执行实体的类型，执行实体的热和功耗。等等 重新配置可以包括但不限于高速缓冲存储器的相关性，可用于存储数据的高速缓冲存储器的量，高速缓冲存储器的相干粒度，高速缓存存储器的行大小等。
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公开(公告)号：US20100138571A1
公开(公告)日：2010-06-03
申请号：US12623496
申请日：2009-11-23
申请人： Harold Wade Cain, III , Rui Hou , Xiaowei Shen , Huayong Wang
发明人： Harold Wade Cain, III , Rui Hou , Xiaowei Shen , Huayong Wang
CPC分类号： G06F9/30087 , G06F9/467 , G06F9/5016
摘要： A system, method, and computer readable article of manufacture for sharing buffer management. The system includes: a predictor module to predict at runtime a transaction data size of a transaction according to history information of the transaction; and a resource management module to allocate sharing buffer resources for the transaction according to the predicted transaction data size in response to beginning of the transaction, to record an actual sharing buffer size occupied by the transaction in response to the successful commitment of the transaction, and to update the history information of the transaction.
摘要翻译： 用于共享缓冲区管理的系统，方法和计算机可读制造品。 该系统包括：预测器模块，用于根据交易的历史信息在运行时预测交易的交易数据大小; 以及资源管理模块，用于响应于所述事务的开始，根据预测的事务数据大小来分配所述事务的共享缓冲器资源，以响应所述事务的成功承诺来记录所述事务所占用的实际共享缓冲区大小;以及 更新交易的历史信息。
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