发明申请
US20090265672A1 METHOD AND SYSTEM FOR ENTRY AND VERIFICATION OF PARASITIC DESIGN CONSTRAINTS FOR ANALOG INTEGRATED CIRCUITS
有权
用于模拟集成电路的PARASITIC设计约束的输入和验证方法与系统
- 专利标题： METHOD AND SYSTEM FOR ENTRY AND VERIFICATION OF PARASITIC DESIGN CONSTRAINTS FOR ANALOG INTEGRATED CIRCUITS
- 专利标题（中）： 用于模拟集成电路的PARASITIC设计约束的输入和验证方法与系统
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申请号： US12103961申请日： 2008-04-16
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公开(公告)号： US20090265672A1公开(公告)日： 2009-10-22
- 发明人: Ian St.John , Mohamed Kamal Mahmoud , Baher S. Haroun
- 申请人： Ian St.John , Mohamed Kamal Mahmoud , Baher S. Haroun
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on a set of specifications, (2) attaching parasitic constraints to the schematic, (3) creating a layout of the analog integrated circuit based on the schematic including the parasitic constraints, (4) extracting parasitic values from parasitic elements of the layout and (5) comparing the extracted parasitic values with the parasitic constraints to verify compliance therewith.