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    METHOD AND SYSTEM FOR ENTRY AND VERIFICATION OF PARASITIC DESIGN CONSTRAINTS FOR ANALOG INTEGRATED CIRCUITS
    1.
    发明申请
    METHOD AND SYSTEM FOR ENTRY AND VERIFICATION OF PARASITIC DESIGN CONSTRAINTS FOR ANALOG INTEGRATED CIRCUITS 有权
    用于模拟集成电路的PARASITIC设计约束的输入和验证方法与系统

    公开(公告)号：US20090265672A1

    公开(公告)日：2009-10-22

    申请号：US12103961

    申请日：2008-04-16

    申请人： Ian St.John ,  Mohamed Kamal Mahmoud ,  Baher S. Haroun

    发明人： Ian St.John ,  Mohamed Kamal Mahmoud ,  Baher S. Haroun

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5063

    摘要： A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on a set of specifications, (2) attaching parasitic constraints to the schematic, (3) creating a layout of the analog integrated circuit based on the schematic including the parasitic constraints, (4) extracting parasitic values from parasitic elements of the layout and (5) comparing the extracted parasitic values with the parasitic constraints to verify compliance therewith.

    摘要翻译： 设计模拟集成电路（IC）的方法，寄生约束分析器和确定模拟IC的布局的方法符合寄生约束。 在一个实施例中，设计模拟IC的方法包括：（1）基于一组规范创建模拟集成电路的示意图，（2）将附加约束附加到原理图，（3）创建模拟 基于包括寄生约束的示意图的集成电路，（4）从布局的寄生元件提取寄生值，以及（5）将所提取的寄生值与寄生约束进行比较以验证其符合性。

    Method and system for entry and verification of parasitic design constraints for analog integrated circuits
    2.
    发明授权
    Method and system for entry and verification of parasitic design constraints for analog integrated circuits 有权
    用于模拟集成电路寄生设计约束的输入和验证的方法和系统

    公开(公告)号：US08209650B2

    公开(公告)日：2012-06-26

    申请号：US12103961

    申请日：2008-04-16

    申请人： Ian St. John ,  Mohamed Kamal Mahmoud ,  Baher S. Haroun

    发明人： Ian St. John ,  Mohamed Kamal Mahmoud ,  Baher S. Haroun

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5063

    摘要： A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on a set of specifications, (2) attaching parasitic constraints to the schematic, (3) creating a layout of the analog integrated circuit based on the schematic including the parasitic constraints, (4) extracting parasitic values from parasitic elements of the layout and (5) comparing the extracted parasitic values with the parasitic constraints to verify compliance therewith.

    摘要翻译： 设计模拟集成电路（IC）的方法，寄生约束分析器和确定模拟IC的布局的方法符合寄生约束。 在一个实施例中，设计模拟IC的方法包括：（1）基于一组规范创建模拟集成电路的示意图，（2）将附加约束附加到原理图，（3）创建模拟 基于包括寄生约束的示意图的集成电路，（4）从布局的寄生元件提取寄生值，以及（5）将所提取的寄生值与寄生约束进行比较以验证其符合性。

    ANALOG BASEBAND CIRCUIT FOR A TERAHERTZ PHASED ARRAY SYSTEM
    4.
    发明申请
    ANALOG BASEBAND CIRCUIT FOR A TERAHERTZ PHASED ARRAY SYSTEM 有权
    用于TERAHERTZ相位阵列的模拟基带电路

    公开(公告)号：US20120261579A1

    公开(公告)日：2012-10-18

    申请号：US13085264

    申请日：2011-04-12

    申请人： Srinath M. Ramaswamy ,  Vijay B. Rentala ,  Brian P. Ginsburg ,  Baher S. Haroun ,  Eunyoung Seok

    发明人： Srinath M. Ramaswamy ,  Vijay B. Rentala ,  Brian P. Ginsburg ,  Baher S. Haroun ,  Eunyoung Seok

    IPC分类号： G01J5/26 ,  G01J5/02

    CPC分类号： H01Q3/26 ,  G01S7/288 ,  G01S13/426

    摘要： A method for determining the position of a target is provided. Several emitted pulses of terahertz radiations are emitted from a phased array (which has several transceivers) in consecutive cycles (typically). These emitted pulses are generally configured to be reflected by a target so as to be received by the phased array within a scan range (which includes a digitization window with several sampling periods). Output signals from each of the transceivers are then combined to generate a combined signal for each cycle. The combined signal in each sampling period within the digitization window for emitted pulses is averaged to generate an averaged signal for each sampling period within the digitization window. These averaged signals are then digitized.

    摘要翻译： 提供了一种用于确定目标位置的方法。 几个发射的太赫兹辐射脉冲从相控阵列（其具有几个收发器）以连续的周期（通常）发射。 这些发射脉冲通常被配置为被目标物反射，以便在扫描范围内包括相控阵列（其包括具有多个采样周期的数字化窗口）。 然后将来自每个收发器的输出信号组合以产生每个周期的组合信号。 在发射脉冲的数字化窗口内的每个采样周期中的组合信号被平均以产生数字化窗口内的每个采样周期的平均信号。 然后将这些平均信号数字化。

    DOWNCONVERSION MIXER
    6.
    发明申请
    DOWNCONVERSION MIXER 有权
    DOWNCONVERSION混合器

    公开(公告)号：US20120049972A1

    公开(公告)日：2012-03-01

    申请号：US12871626

    申请日：2010-08-30

    申请人： Brian P. Ginsburg ,  Vijay B. Rentala ,  Srinath M. Ramaswamy ,  Baher S. Haroun ,  Eunyoung Seok

    发明人： Brian P. Ginsburg ,  Vijay B. Rentala ,  Srinath M. Ramaswamy ,  Baher S. Haroun ,  Eunyoung Seok

    IPC分类号： H01P1/10 ,  H01P5/18

    CPC分类号： H01P5/184 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/165 ,  H03D2200/0023

    摘要： At very high frequencies, generally above 100 GHz, the performance of traditional radio frequency (RF) circuitry begins to significantly limit performance. An example is the hybrid coupler, which can have a relatively narrow 90° bandwidth in these frequency ranges. Here, however, a branch-line hybrid coupler (which has been integrated into a quadrature downconversion mixer) has been modified. Namely, an adjustable impedance network has been coupled to isolation port (which has traditionally been terminated) to substantially increase the tuning range and expand the bandwidth of the quadrature mixer within these very high frequency ranges.

    摘要翻译： 在非常高的频率（通常在100GHz以上），传统射频（RF）电路的性能开始显着地限制性能。 一个例子是混合耦合器，其在这些频率范围内可以具有相对窄的90°带宽。 然而，这里已经修改了分支线路混合耦合器（其已被集成到正交下变频混频器中）。 也就是说，可调阻抗网络已经耦合到隔离端口（传统上已被终止），以显着增加调谐范围并且在这些非常高的频率范围内扩大正交混频器的带宽。

    TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS
    8.
    发明申请
    TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS 有权
    用于IEEE 1149.1测试访问端口的多个光纤扫描接入的TAP和链接模块

    公开(公告)号：US20100162061A1

    公开(公告)日：2010-06-24

    申请号：US12539373

    申请日：2009-08-11

    申请人： Baher S. Haroun ,  Lee D. Whetsel

    发明人： Baher S. Haroun ,  Lee D. Whetsel

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318558 ,  G11C29/46

    摘要： An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

    摘要翻译： 描述了用于在集成电路上测试多个电路的架构。 该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

    TAP and linking module for scan access of multiple cores with IEEE 1149.1 test access ports
    9.
    发明授权
    TAP and linking module for scan access of multiple cores with IEEE 1149.1 test access ports 有权
    TAP和连接模块，用于具有IEEE 1149.1测试访问端口的多个核心的扫描访问

    公开(公告)号：US06324662B1

    公开(公告)日：2001-11-27

    申请号：US09277504

    申请日：1999-03-26

    申请人： Baher S. Haroun ,  Lee D. Whetsel

    发明人： Baher S. Haroun ,  Lee D. Whetsel

    IPC分类号： G01R3128

    CPC分类号： G01R31/318536 ,  G01R31/318555 ,  G01R31/318563

    摘要： An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

    摘要翻译： 描述了用于在集成电路上测试多个电路的架构。 该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

    Data compression using bit change statistics
    10.
    发明授权
    Data compression using bit change statistics 失效
    使用位变化统计数据压缩

    公开(公告)号：US6038536A

    公开(公告)日：2000-03-14

    申请号：US16615

    申请日：1998-01-30

    申请人： Baher S. Haroun ,  Suman Narayan

    发明人： Baher S. Haroun ,  Suman Narayan

    IPC分类号： G10L19/00 ,  H03M7/30 ,  G10L5/02 ,  G11B5/00

    CPC分类号： G10L19/002 ,  H03M7/30

    摘要： A method is provided for compressing relatively time invariant binary data, such as speech data in a telephone answering device, using statistical analysis of changes in the data. An original record organized into multiple frames of multiple bits each is used to construct an XORed record of the same number of frames and bits. The XORed record has a base frame with the same bit value pattern as a corresponding base frame of the original record, and remaining frames with bit values given by the outputs of an exclusive-OR operation applied to the bit values of corresponding and prior frames of the original record. The bit positions of the XORed record frame set are analyzed and reordered, according to their bit value change activity and used to construct an output record. The output record may have a base frame with the same bit value pattern as the corresponding reordered XORed record base frame. Other output record frames are established using a compression scheme wherein at least low bit value change subframes of the reordered XORed record frames are compressed by replacing them with shorter bit patterns having a format comprising a first part representing the number of bit changes occurring in the subframe and a second part identifying the location or locations, if any, of those changes. The foregoing procedure is reversed to restore the original record from the output record.

    摘要翻译： 提供一种用于使用数据中的变化的统计分析来压缩相对时间不变二进制数据的方法，诸如电话应答设备中的语音数据。 组织成多个多个位的原始记录各自用于构造相同数量的帧和位的异或记录。 异或记录具有与原始记录的相应基本帧相同的比特值模式的基本帧，并且具有由异或运算的输出给出的比特值的剩余帧应用于相应和先前帧的比特值 原始记录。 根据其位值变化活动对异或记录帧集合的位位置进行分析和重新排序，并用于构建输出记录。 输出记录可以具有与相应的重新排序的异或记录基本帧相同的比特值模式的基本帧。 使用压缩方案建立其他输出记录帧，其中通过用具有包括表示在子帧中发生的位改变的数量的第一部分的格式的较短位模式来替换它们来压缩重新排序的异或记录帧的至少低位值改变子帧 以及识别这些改变的位置或位置（如果有的话）的第二部分。 上述过程相反，以从输出记录恢复原始记录。