发明申请
US20090269865A1 Method for PMOS Device Processing Using a Polysilicon Footing Characteristic to Achieve Low Leakage
有权
使用多晶硅底脚特征实现低漏电的PMOS器件处理方法
- 专利标题： Method for PMOS Device Processing Using a Polysilicon Footing Characteristic to Achieve Low Leakage
- 专利标题（中）： 使用多晶硅底脚特征实现低漏电的PMOS器件处理方法
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申请号： US12238689申请日： 2008-09-26
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公开(公告)号： US20090269865A1公开(公告)日： 2009-10-29
- 发明人: Chia Hao Lee
- 申请人： Chia Hao Lee
- 申请人地址： CN Shanghai
- 专利权人： Semiconductor Manufacturing International (Shanghai) Corporation
- 当前专利权人： Semiconductor Manufacturing International (Shanghai) Corporation
- 当前专利权人地址： CN Shanghai
- 优先权： CN200810036944.9 20080428
- 主分类号： H01L21/28
- IPC分类号： H01L21/28 ; H01L21/66
摘要：
A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is characterized by a thickness, a width and a polysilicon footing profile. In a specific embodiment, the method performs a TCAD simulation and determines a response of device performance due to the polysilicon footing profile from the model. The method uses the model to provide a process control window for fabricating the polysilicon gate.
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