发明申请
- 专利标题: DELAY LOCKED LOOP CIRCUIT AND DELAY LOCKING METHOD
- 专利标题(中): 延迟锁定环路延迟锁定方法
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申请号: US12332295申请日: 2008-12-10
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公开(公告)号: US20090278578A1公开(公告)日: 2009-11-12
- 发明人: Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
- 申请人: Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
- 申请人地址: KR Ichon
- 专利权人: HYNIX SEMICONDUCTOR, INC.
- 当前专利权人: HYNIX SEMICONDUCTOR, INC.
- 当前专利权人地址: KR Ichon
- 优先权: KR10-2008-0043023 20080508
- 主分类号: H03L7/06
- IPC分类号: H03L7/06
摘要:
A delay locked loop circuit includes a phase detecting unit for detecting a phase difference between a reference clock signal and a feedback clock signal, and for producing a phase difference detection signal, a code generating unit for producing a digital code signal according to the phase difference detection signal, a control current generating unit for generating a control current using the digital code signal, and a current controlled delay line for producing the feedback clock signal by delaying the reference clock signal by a delay time varied by the control current.
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