发明申请
- 专利标题： CIRCUIT BOARD WITH BURIED CONDUCTIVE TRACE FORMED THEREON AND METHOD FOR MANUFACTURING THE SAME
- 专利标题（中）： 形成有导电导线的电路板及其制造方法
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申请号： US12422629申请日： 2009-04-13
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公开(公告)号： US20090288861A1公开(公告)日： 2009-11-26
- 发明人: Guo Cheng LIAO
- 申请人： Guo Cheng LIAO
- 申请人地址： TW Kaohsiung
- 专利权人： ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- 当前专利权人： ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- 当前专利权人地址： TW Kaohsiung
- 优先权： TW097119024 20080523
- 主分类号： H05K1/02
- IPC分类号： H05K1/02 ; H05K3/00
摘要：
A circuit board with a buried conductive trace formed thereon according to the present invention is provided. A buried conductive trace layer is formed on the surface of a substrate and the pads of the conductive trace layer are plated with a layer of copper so that the pads are heightened to facilitate the subsequent process of molding.
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