发明申请
- 专利标题: HARDWARE ENGINE TO DEMOD SIMO, MIMO, AND SDMA SIGNALS
- 专利标题(中): 硬件引擎解析SIMO,MIMO和SDMA信号
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申请号: US12408603申请日: 2009-03-20
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公开(公告)号: US20090304116A1公开(公告)日: 2009-12-10
- 发明人: Raghu N. Challa , Hemanth Sampath , Gwendolyn D. Barriac
- 申请人: Raghu N. Challa , Hemanth Sampath , Gwendolyn D. Barriac
- 申请人地址: US CA San Diego
- 专利权人: QUALCOMM Incorporated
- 当前专利权人: QUALCOMM Incorporated
- 当前专利权人地址: US CA San Diego
- 主分类号: H04L27/06
- IPC分类号: H04L27/06
摘要:
An apparatus including a configurable demodulation architecture which includes a control module and a demodulation engine. The control module includes a set of one or more control fields. The demodulation engine includes a spatial whitening module, a Minimum Mean Square Estimation (MMSE) module, at least a first Maximal Ratio Combining (MRC) module, and at least one multiplexer. Further, the multiplexer is coupled to the instruction module and controlled based on the control fields to select at least one of the MMSE module or MRC module.
公开/授权文献
- US08995590B2 Hardware engine to demod SIMO, MIMO, and SDMA signals 公开/授权日:2015-03-31
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