发明申请
US20090310728A1 IN-SITU JITTER TOLERANCE TESTING FOR SERIAL INPUT OUTPUT
有权
用于串行输入输出的IN-SITU JITTER耐力测试
- 专利标题： IN-SITU JITTER TOLERANCE TESTING FOR SERIAL INPUT OUTPUT
- 专利标题（中）： 用于串行输入输出的IN-SITU JITTER耐力测试
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申请号： US12139835申请日： 2008-06-16
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公开(公告)号： US20090310728A1公开(公告)日： 2009-12-17
- 发明人: James E. Jaussi , Bryan K. Casper , Stephen R. Mooney
- 申请人： James E. Jaussi , Bryan K. Casper , Stephen R. Mooney
- 主分类号： H04L7/00
- IPC分类号： H04L7/00
摘要：
According to some embodiments, a method and apparatus are provided to generate a sine wave via a jitter modulator to modulate a control voltage of a clock source. The jitter modulator is in-situ on a die. The sine wave is received at a clock and data recovery circuit comprising the clock source. The clock and data recovery circuit is in-situ on the die.
公开/授权文献
- US08249137B2 In-situ jitter tolerance testing for serial input output 公开/授权日：2012-08-21
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