发明申请
US20100040182A1 BUST-MODE CLOCK AND DATA RECOVERY CIRCUIT USING PHASE SELECTING TECHNOLOGY
有权
使用相位选择技术的BUST模式时钟和数据恢复电路
- 专利标题: BUST-MODE CLOCK AND DATA RECOVERY CIRCUIT USING PHASE SELECTING TECHNOLOGY
- 专利标题(中): 使用相位选择技术的BUST模式时钟和数据恢复电路
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申请号: US12266530申请日: 2008-11-06
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公开(公告)号: US20100040182A1公开(公告)日: 2010-02-18
- 发明人: Ching-Yuan Yang , Jung-Mao Lin , Yu-Min Lin
- 申请人: Ching-Yuan Yang , Jung-Mao Lin , Yu-Min Lin
- 申请人地址: TW Hsinchu
- 专利权人: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- 当前专利权人: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- 当前专利权人地址: TW Hsinchu
- 优先权: TW97131222 20080815
- 主分类号: H04L7/00
- IPC分类号: H04L7/00
摘要:
A bust-mode clock and data recovery circuit using phase selecting technology is provided. In the data recovery circuit, a phase-locked loop (PLL) circuit is used for providing a plurality of fixed clock signals, each of which has a clock phase. An oversampling phase selecting circuit is coupled to the phase-locked loop circuit and used for detecting a data edge of a received data signal by using the clock signals and selects a clock phase to be locked according to the location of the data edge. A delay-locked loop (DLL) circuit is coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, and used for comparing the data phase of the data signal with the clock phase of the selected clock signal, so as to delay the data phase of the data signal by a delay time until the data phase is locked as the clock phase.