An electronic device is disclosed comprising a transceiver stage (140) for communicating signals between the electronic device and a further device; and a baseband processor arrangement (120) implementing a built-in self test arrangement for testing the transceiver channels of the electronic device (100). The built-in self test arrangement further comprises a plurality of records, each record comprising predetermined response deviations to different test signals caused by a parametric fault; and means for selecting those records from the plurality of records for which the predetermined response deviation corresponds to the deviation of the received response. The present invention is based on the realization that a deviation of a response to a test signal from an expected value is dependent on specific parametric faults in specific components in the test signal path and, in addition, on the shape of the test signal. This information is stored in the BIST arrangement and is used to identify a parametric fault, if present, by subjecting the electronic device to a series of test signals.