发明申请
US20100057825A1 METHOD AND ELECTRONIC COMPUTING CIRCUIT FOR OPERAND WIDTH REDUCTION FOR A MODULO ADDER FOLLOWED BY SATURATION CONCURRENT MESSAGE PROCESSING
失效
方法和电子计算电路，用于通过饱和同步信息处理进行模块化增加的操作宽度减小
- 专利标题： METHOD AND ELECTRONIC COMPUTING CIRCUIT FOR OPERAND WIDTH REDUCTION FOR A MODULO ADDER FOLLOWED BY SATURATION CONCURRENT MESSAGE PROCESSING
- 专利标题（中）： 方法和电子计算电路，用于通过饱和同步信息处理进行模块化增加的操作宽度减小
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申请号： US12028889申请日： 2008-02-11
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公开(公告)号： US20100057825A1公开(公告)日： 2010-03-04
- 发明人: Tobias Gemmeke , Nicolas Maeding , Jochen Preiss
- 申请人： Tobias Gemmeke , Nicolas Maeding , Jochen Preiss
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 优先权： EP07102221.4 20070213
- 主分类号： G06F7/50
- IPC分类号： G06F7/50
摘要：
A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A′, B′) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A′, B′) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit (1, 5) is described performing said method. Additionally a computer system comprising such an electronic computing circuit is described.