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1.发明授权Electronic computing circuit for operand width reduction for a modulo adder followed by saturation concurrent message processing 失效用于模加法器的操作数宽度减小的电子计算电路，然后进行饱和并发消息处理公开(公告)号：US08370409B2
公开(公告)日：2013-02-05
申请号：US12028889
申请日：2008-02-11
申请人： Tobias Gemmeke , Nicolas Maeding , Jochen Preiss
发明人： Tobias Gemmeke , Nicolas Maeding , Jochen Preiss
IPC分类号： G06F7/00
摘要： A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A′, B′) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A′, B′) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit (1, 5) is described performing said method. Additionally a computer system comprising such an electronic computing circuit is described.
摘要翻译： 描述了一种操作数宽度减小的方法，其中处理位宽N为N的两个N位输入操作数（A，B），并减少位宽M的M位输出操作数（A'，B'） 以一种方式产生，包括在所述两个M位输出操作数（A'，B'）上执行的对M位进行饱和后的M位加法器功能的后处理提供等于M的M位结果 两个N位输入操作数（A，B）的N位模加法器功能的比特结果，后跟饱和至M位。 进一步描述执行所述方法的电子计算电路（1,5）。 另外，描述了包括这种电子计算电路的计算机系统。
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2.发明申请METHOD AND ELECTRONIC COMPUTING CIRCUIT FOR OPERAND WIDTH REDUCTION FOR A MODULO ADDER FOLLOWED BY SATURATION CONCURRENT MESSAGE PROCESSING 失效方法和电子计算电路，用于通过饱和同步信息处理进行模块化增加的操作宽度减小公开(公告)号：US20100057825A1
公开(公告)日：2010-03-04
申请号：US12028889
申请日：2008-02-11
申请人： Tobias Gemmeke , Nicolas Maeding , Jochen Preiss
发明人： Tobias Gemmeke , Nicolas Maeding , Jochen Preiss
IPC分类号： G06F7/50
摘要： A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A′, B′) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A′, B′) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit (1, 5) is described performing said method. Additionally a computer system comprising such an electronic computing circuit is described.
摘要翻译： 描述了一种操作数宽度减小的方法，其中处理位宽N为N的两个N位输入操作数（A，B），并减少位宽M的M位输出操作数（A'，B'） 以一种方式产生，包括在所述两个M位输出操作数（A'，B'）上执行的对M位进行饱和后的M位加法器功能的后处理提供等于M的M位结果 两个N位输入操作数（A，B）的N位模加法器功能的比特结果，后跟饱和至M位。 进一步描述执行所述方法的电子计算电路（1,5）。 另外，描述了包括这种电子计算电路的计算机系统。
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3.发明授权Method and apparatus for performing equivalence checking on circuit designs having differing clocking and latching schemes 失效对具有不同时钟和锁存方案的电路设计进行等价性检查的方法和装置公开(公告)号：US07624363B2
公开(公告)日：2009-11-24
申请号：US11679234
申请日：2007-02-27
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing equivalence checking on logic circuit designs is disclosed. Within a composite netlist of an original version and a modified version of a logic circuit design, all level-sensitive sequential elements sensitized by a clock=0 are converted into buffers, and all level-sensitive sequential elements sensitized by a clock=1 are converted into level-sensitive registers. A subset of edge-sensitive sequential elements are selectively transformed into level-sensitive sequential elements by removing edge detection logic from the subset of the edge-sensitive sequential elements. A clock to the resulting sequential elements is then set to a logical “1” to verify the sequential equivalence of the transformed netlist.
摘要翻译： 公开了一种用于对逻辑电路设计进行等价性检查的方法。 在原始版本的复合网表和逻辑电路设计的修改版本中，由时钟= 0敏感的所有电平敏感顺序元件都转换为缓冲器，并且转换为由时钟= 1敏感的所有电平敏感顺序元件 进入电平敏感寄存器。 通过从边缘敏感顺序元素的子集中去除边缘检测逻辑，边缘敏感顺序元素的子集被选择性地变换成等级敏感的顺序元素。 然后将产生的顺序元素的时钟设置为逻辑“1”，以验证转换的网表的顺序等价。
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4.发明授权Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance 失效具有指示结果的指令特征位的指令集架构不具有架构重要性公开(公告)号：US08266411B2
公开(公告)日：2012-09-11
申请号：US12366169
申请日：2009-02-05
IPC分类号： G06F9/30
CPC分类号： G06F9/30076 , G06F9/30185 , G06F9/30192 , G06F9/3832 , G06F9/3838 , G06F9/384 , G06F9/3861
摘要： Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor.
摘要翻译： 改进的处理器代替具有包括固定架构操作数的指令集体系结构（ISA）的处理器，而不是用于计算指令（例如，乘法加载/存储指令）的附加特征位。 这些特定指令的附加位影响处理器对这些指令的处理。 另外，引入了新的指令来进一步使用所提出的方法。 通常，这些附加特征位以及指令可以由编译器自动生成，以为处理器提供相对适合的指令序列。
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5.发明授权Method of operand width reduction to enable usage of narrower saturation adder 失效操作数宽度缩减方法可以使用较窄的饱和加法器公开(公告)号：US07962538B2
公开(公告)日：2011-06-14
申请号：US11560165
申请日：2006-11-15
申请人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Kerstin Schelm
发明人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Kerstin Schelm
CPC分类号： G06F7/49921
摘要： An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M
摘要翻译： 一种电子计算电路，用于实现一种将比特长度N减小到比特长度M的两个操作数的比特宽度的方法，因此，M
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6.发明申请Method and Apparatus for Performing Equivalence Checking on Circuit Designs Having Differing Clocking and Latching Schemes 失效具有不同时钟和锁存方案的电路设计的等效性检查方法和装置公开(公告)号：US20080209287A1
公开(公告)日：2008-08-28
申请号：US11679234
申请日：2007-02-27
IPC分类号： G01R31/28
CPC分类号： G06F17/504
摘要： A method for performing equivalence checking on logic circuit designs is disclosed. Within a composite netlist of an original version and a modified version of a logic circuit design, all level-sensitive sequential elements sensitized by a clock=0 are converted into buffers, and all level-sensitive sequential elements sensitized by a clock=1 are converted into level-sensitive registers. A subset of edge-sensitive sequential elements are selectively transformed into level-sensitive sequential elements by removing edge detection logic from the subset of the edge-sensitive sequential elements. A clock to the resulting sequential elements is then set to a logical “1” to verify the sequential equivalence of the transformed netlist.
摘要翻译： 公开了一种用于对逻辑电路设计进行等价性检查的方法。 在原始版本的复合网表和逻辑电路设计的修改版本中，由时钟= 0敏感的所有电平敏感顺序元件都转换为缓冲器，并且转换为由时钟= 1敏感的所有电平敏感顺序元件 进入电平敏感寄存器。 通过从边缘敏感顺序元素的子集中去除边缘检测逻辑，边缘敏感顺序元素的子集被选择性地变换成等级敏感的顺序元素。 然后将产生的顺序元素的时钟设置为逻辑“1”，以验证转换的网表的顺序等价。
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公开(公告)号：US07890901B2
公开(公告)日：2011-02-15
申请号：US11684899
申请日：2007-03-12
申请人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Hari Mony
发明人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Hari Mony
CPC分类号： G06F17/504
摘要： The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding special wrappers (Wrapper A, Wrapper B), and used to equalize the timing of pairs of selected input signals and selected output signals of the logic designs. The wrappers drive certain signals of the designs that are not relevant for actual comparison, such signals including clock signals, clock control signals, scan-path signals, scan-path control signals, and reset signals. In a preferred embodiment, HDL descriptions of logic designs are analyzed. Based on this analysis, the wrappers are implemented as changes to the HDL descriptions. In another embodiment, RTL and/or gate-level netlists are analyzed and modified.
摘要翻译： 比较了数字电路的等效设计的自动验证，其中以不同的硬件描述语言（HDL）实现的逻辑设计和不同的设计方法进行了比较。 通过添加特殊包装器（Wrapper A，Wrapper B）来修改设计（代码A，代码B），并用于均衡所选输入信号对的时序和逻辑设计的选定输出信号。 封装器驱动与实际比较无关的设计的某些信号，包括时钟信号，时钟控制信号，扫描路径信号，扫描路径控制信号和复位信号等信号。 在优选实施例中，分析逻辑设计的HDL描述。 基于这种分析，包装器被实现为对HDL描述的改变。 在另一个实施例中，分析和修改RTL和/或门级网表。
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公开(公告)号：US20100199074A1
公开(公告)日：2010-08-05
申请号：US12366169
申请日：2009-02-05
IPC分类号： G06F9/30
CPC分类号： G06F9/30076 , G06F9/30185 , G06F9/30192 , G06F9/3832 , G06F9/3838 , G06F9/384 , G06F9/3861
摘要： Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor.
摘要翻译： 改进的处理器代替具有包括固定架构操作数的指令集体系结构（ISA）的处理器，而不是用于计算指令（例如，乘法加载/存储指令）的附加特征位。 这些特定指令的附加位影响处理器对这些指令的处理。 此外，引入了新的指令以进一步使用所提出的方法。 通常，这些附加特征位以及指令可以由编译器自动生成，以为处理器提供相对适合的指令序列。
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公开(公告)号：US20080288901A1
公开(公告)日：2008-11-20
申请号：US12107940
申请日：2008-04-23
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/505 , G06F2217/78
摘要： The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved.
摘要翻译： 本发明提供了一种全自动的方法，用于获得由于时钟选通而具有最小功耗的电路。 要优化的电路设计被修改为减少功率修改的设计并且与时钟门控方案相关联。 验证工具将修改后的设计与原始设计进行比较，以确定是否可以使用修改后的设计。 可以重复进行进一步的修改，直到实现最佳设计。
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公开(公告)号：US20070226664A1
公开(公告)日：2007-09-27
申请号：US11684899
申请日：2007-03-12
申请人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Hari Mony
发明人： Tobias Gemmeke , Jens Leenstra , Nicolas Maeding , Hari Mony
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding special wrappers (Wrapper A, Wrapper B), and used to equalize the timing of pairs of selected input signals and selected output signals of the logic designs. The wrappers drive certain signals of the designs that are not relevant for actual comparison, such signals including clock signals, clock control signals, scan-path signals, scan-path control signals, and reset signals. In a preferred embodiment, HDL descriptions of logic designs are analyzed. Based on this analysis, the wrappers are implemented as changes to the HDL descriptions. In another embodiment, RTL and/or gate-level netlists are analyzed and modified.
摘要翻译： 比较了数字电路的等效设计的自动验证，其中以不同的硬件描述语言（HDL）实现的逻辑设计和不同的设计方法进行了比较。 通过添加特殊包装器（Wrapper A，Wrapper B）来修改设计（代码A，代码B），并用于均衡所选输入信号对的时序和逻辑设计的选定输出信号。 封装器驱动与实际比较无关的设计的某些信号，包括时钟信号，时钟控制信号，扫描路径信号，扫描路径控制信号和复位信号等信号。 在优选实施例中，分析逻辑设计的HDL描述。 基于这种分析，包装器被实现为对HDL描述的改变。 在另一个实施例中，分析和修改RTL和/或门级网表。
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