发明申请
US20100070232A1 METHOD AND SYSTEM FOR GENERATING AN INTEGRATED CIRCUIT CHIP FACILITY WAVEFORM FROM A SERIES OF CHIP SNAPSHOTS
失效
用于从一系列芯片插座产生集成电路芯片设备波形的方法和系统
- 专利标题： METHOD AND SYSTEM FOR GENERATING AN INTEGRATED CIRCUIT CHIP FACILITY WAVEFORM FROM A SERIES OF CHIP SNAPSHOTS
- 专利标题（中）： 用于从一系列芯片插座产生集成电路芯片设备波形的方法和系统
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申请号： US12211129申请日： 2008-09-16
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公开(公告)号： US20100070232A1公开(公告)日： 2010-03-18
- 发明人: Rolf Fritz , Andreas Koenig , Christopher Smith , Manfred Walz
- 申请人： Rolf Fritz , Andreas Koenig , Christopher Smith , Manfred Walz
- 主分类号： G06F17/00
- IPC分类号： G06F17/00 ; H03K5/01
摘要：
Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.
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