公开(公告)号：US08359503B2

公开(公告)日：2013-01-22

申请号：US12211129

申请日：2008-09-16

申请人： Rolf Fritz ,  Andreas Koenig ,  Christopher Smith ,  Manfred Walz

发明人： Rolf Fritz ,  Andreas Koenig ,  Christopher Smith ,  Manfred Walz

IPC分类号： G06F11/00

CPC分类号： G01R31/31707

摘要： Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.

摘要翻译： 用于从一系列芯片快照生成芯片设施波形的方法和相应的测试系统。 所述方法包括：（i）多次测试集成芯片，每次每次确定集成电路的状态保持元件的状态时，增加延迟由触发错误状态产生的时钟脉冲的时钟延迟，以及（ii）测试集成电路芯片 一次基于状态保持元件的先前状态产生误差条件并确定多次集成电路的状态保持元件的状态。

公开(公告)号：US20100070232A1

公开(公告)日：2010-03-18

申请号：US12211129

申请日：2008-09-16

申请人： Rolf Fritz ,  Andreas Koenig ,  Christopher Smith ,  Manfred Walz

发明人： Rolf Fritz ,  Andreas Koenig ,  Christopher Smith ,  Manfred Walz

IPC分类号： G06F17/00 ,  H03K5/01

CPC分类号： G01R31/31707

摘要： Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.

摘要翻译： 用于从一系列芯片快照生成芯片设施波形的方法和相应的测试系统。 所述方法包括：（i）多次测试集成芯片，每次每次确定集成电路的状态保持元件的状态时，增加延迟由触发错误状态产生的时钟脉冲的时钟延迟，以及（ii）测试集成电路芯片 一次基于状态保持元件的先前状态产生误差条件并确定多次集成电路的状态保持元件的状态。

公开(公告)号：US20130212445A1

公开(公告)日：2013-08-15

申请号：US13397544

申请日：2012-02-15

申请人： Martin Doerr ,  Benedikt Geukes ,  Holger Horbach ,  Matteo Michel ,  Manfred Walz

发明人： Martin Doerr ,  Benedikt Geukes ,  Holger Horbach ,  Matteo Michel ,  Manfred Walz

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/3177 ,  G01R31/318552 ,  G01R31/318572 ,  G06F11/267

摘要： A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.

摘要翻译： 用于微处理器的扫描电路（JTAG 1149扩展）利用以比外部JTAG时钟更快的时钟速度工作的传输逻辑和扫描链。 传输逻辑将输入串行数据流（TDI）转换成输入数据包，将其发送到扫描链，并将输出数据包转换为输出数据流（TDO）。 传输逻辑包括具有分片输入缓冲器的解串器和具有分片输出缓冲器的串行器。 扫描电路可用于边界扫描锁存器的测试，或用于控制微处理器的内部功能。 本地时钟缓冲器可用于分配时钟信号，由外部时钟过采样产生的信号控制。 结果是JTAG扫描系统不受外部JTAG时钟速度的限制，允许多个内部扫描操作在单个外部JTAG周期内完成。

公开(公告)号：US08914693B2

公开(公告)日：2014-12-16

申请号：US13397544

申请日：2012-02-15

申请人： Martin Doerr ,  Benedikt Geukes ,  Holger Horbach ,  Matteo Michel ,  Manfred Walz

发明人： Martin Doerr ,  Benedikt Geukes ,  Holger Horbach ,  Matteo Michel ,  Manfred Walz

IPC分类号： G01R31/28 ,  G01R31/3177 ,  G01R31/3185

CPC分类号： G01R31/3177 ,  G01R31/318552 ,  G01R31/318572 ,  G06F11/267

摘要： A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.

摘要翻译： 用于微处理器的扫描电路（JTAG 1149扩展）利用以比外部JTAG时钟更快的时钟速度工作的传输逻辑和扫描链。 传输逻辑将输入串行数据流（TDI）转换成输入数据包，将其发送到扫描链，并将输出数据包转换为输出数据流（TDO）。 传输逻辑包括具有分片输入缓冲器的解串器和具有分片输出缓冲器的串行器。 扫描电路可用于边界扫描锁存器的测试，或用于控制微处理器的内部功能。 本地时钟缓冲器可用于分配时钟信号，由外部时钟过采样产生的信号控制。 结果是JTAG扫描系统不受外部JTAG时钟速度的限制，允许多个内部扫描操作在单个外部JTAG周期内完成。

公开(公告)号：US5388240A

公开(公告)日：1995-02-07

申请号：US751495

申请日：1991-08-29

申请人： Ulrich Olderdissen ,  Manfred Walz

发明人： Ulrich Olderdissen ,  Manfred Walz

IPC分类号： G06F12/04 ,  G06F12/0855 ,  G06F12/0879 ,  G06F12/00 ,  G06F12/06 ,  G06F13/00 ,  G06F13/23

CPC分类号： G06F12/0879 ,  G06F12/04 ,  G06F12/0859

摘要： A data mechanism having a random access memory (RAM) which has a plurality of groups of memory chips, each group being divisible into two equally sized chip sets. Each group of memory chips is addressed by a first address and each individual memory chip is addressed by a second address. The random access memory contains stored data. A cache, connected to the RAM, stores a portion of data stored in the RAM and is accessed by a cache address for separately reading requested data therefrom. The cache provides a cache miss signal when it does not contain the requested data. A CPU, connected to the cache and the RAM, receives the cache miss signal and provides responsive thereto, a starting address to the random access memory for starting a block transfer from the random access memory to the cache in two shots. The starting address includes the first address and the second address. The starting address identifies the group and individual chip within the group which contains the first bit which, when attempted to be read from the cache, caused the cache miss signal. A decoder, connected to the CPU and the random access memory, receives the starting address from the CPU and enables a first block data transfer from a first chip set in a first shot of the two shots starting from said first bit which caused the cache miss signal, and further enables a second block data transfer from a second chip set in a second of the shots.

摘要翻译： 一种具有随机存取存储器（RAM）的数据机制，其具有多组存储器芯片，每组可分为两个相同大小的芯片组。 每组存储器芯片由第一地址寻址，并且每个单独的存储器芯片由第二地址寻址。 随机存取存储器包含存储的数据。 连接到RAM的高速缓存存储存储在RAM中的数据的一部分，并由高速缓存地址访问，用于分别读取所请求的数据。 当高速缓存未包含请求的数据时，缓存提供高速缓存未命中信号。 连接到高速缓存和RAM的CPU接收高速缓存未命中信号，并向其提供起始地址到随机存取存储器，用于在两次镜头中开始从随机存取存储器到高速缓冲存储器的块传送。 起始地址包括第一个地址和第二个地址。 起始地址标识组内包含第一位的组和单独芯片，当尝试从高速缓存读取时，导致高速缓存未命中信号。 连接到CPU和随机存取存储器的解码器从CPU接收起始地址，并且使得能够从所述第一位开始的第一个芯片组中的第一个芯片组中的第一个块数据传输，从导致高速缓存未命中的所述第一个位 信号，并且还使得能够从第二芯片组中的第二个芯片组中的第二块数据传输。

公开(公告)号：US08510072B2

公开(公告)日：2013-08-13

申请号：US12944843

申请日：2010-11-12

申请人： Thomas Buechner ,  Martin Eckert ,  Matthias Klein ,  Manfred Walz ,  Andreas Wagner ,  Gerhard Zilles

发明人： Thomas Buechner ,  Martin Eckert ,  Matthias Klein ,  Manfred Walz ,  Andreas Wagner ,  Gerhard Zilles

IPC分类号： G01R31/00 ,  G01R31/28

CPC分类号： H03K5/19 ,  G01R31/318572

摘要： Additional circuitry is included in an input cell design structure for an integrated circuit to detect and report transitions on an input that was expected to be stable, and to store that event for later analysis. Two or more modified input cells may have their error indications daisy-chained together to minimize additional routing. The storage elements may be included in a scan chain to allow for isolation of which input had the unexpected transition.

摘要翻译： 用于集成电路的输入单元设计结构中包含额外的电路，以检测和报告预期稳定的输入上的转换，并存储该事件供以后分析。 两个或多个修改的输入单元可以将其错误指示菊花链连接在一起以最小化附加路由。 存储元件可以包括在扫描链中，以允许隔离哪个输入具有意想不到的转换。

公开(公告)号：US20120123724A1

公开(公告)日：2012-05-17

申请号：US12944843

申请日：2010-11-12

申请人： Thomas Buechner ,  Martin Eckert ,  Matthias Klein ,  Andreas Wagner ,  Manfred Walz ,  Gerhard Zilles

发明人： Thomas Buechner ,  Martin Eckert ,  Matthias Klein ,  Andreas Wagner ,  Manfred Walz ,  Gerhard Zilles

IPC分类号： G01R31/00 ,  H03K5/153

CPC分类号： H03K5/19 ,  G01R31/318572

摘要： Additional circuitry is included in an input cell design structure for an integrated circuit to detect and report transitions on an input that was expected to be stable, and to store that event for later analysis. Two or more modified input cells may have their error indications daisy-chained together to minimize additional routing. The storage elements may be included in a scan chain to allow for isolation of which input had the unexpected transition.

摘要翻译： 用于集成电路的输入单元设计结构中包含额外的电路，以检测和报告预期稳定的输入上的转换，并存储该事件供以后分析。 两个或多个修改的输入单元可以将其错误指示菊花链连接在一起以最小化附加路由。 存储元件可以包括在扫描链中，以允许隔离哪个输入具有意想不到的转换。