发明申请
- 专利标题: Low Cost Die-To-Wafer Alignment/Bond For 3d IC Stacking
- 专利标题(中): 低成本芯片对晶片对齐/贴合3d IC堆叠
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申请号: US12236967申请日: 2008-09-24
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公开(公告)号: US20100075460A1公开(公告)日: 2010-03-25
- 发明人: Shiqun Gu , Thomas R. Toms
- 申请人: Shiqun Gu , Thomas R. Toms
- 申请人地址: US CA San Diego
- 专利权人: QUALCOMM INCORPORATED
- 当前专利权人: QUALCOMM INCORPORATED
- 当前专利权人地址: US CA San Diego
- 主分类号: H01L21/00
- IPC分类号: H01L21/00
摘要:
The cost associated with alignment in a stacked IC device can be reduced by aligning multiple die instead of a single die during the alignment step. In one embodiment, the alignment structures are placed in the scribe line instead of within the die itself. Aligning four die instead of one eliminates the need for as many alignment indicators and thus more silicon on the wafer can be used for active areas. In addition, this method allows for yield improvement through binning of dies having the same yield configuration.
公开/授权文献
- US08796073B2 Low cost die-to-wafer alignment/bond for 3d IC stacking 公开/授权日:2014-08-05