发明申请
- 专利标题: PAIR BIT LINE PROGRAMMING TO IMPROVE BOOST VOLTAGE CLAMPING
- 专利标题(中): 配对线编程,以提高升压钳位
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申请号: US12398368申请日: 2009-03-05
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公开(公告)号: US20100110792A1公开(公告)日: 2010-05-06
- 发明人: Jeffrey W. Lutze , Deepanshu Dutta
- 申请人: Jeffrey W. Lutze , Deepanshu Dutta
- 主分类号: G11C16/04
- IPC分类号: G11C16/04 ; G11C16/06
摘要:
A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.
公开/授权文献
- US08130556B2 Pair bit line programming to improve boost voltage clamping 公开/授权日:2012-03-06
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