公开(公告)号：US08248850B2

公开(公告)日：2012-08-21

申请号：US12695918

申请日：2010-01-28

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yan Li

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yan Li

IPC分类号： G11C16/06 ,  G11C7/10

CPC分类号： G11C11/5628 ,  G11C16/3418 ,  G11C29/00 ,  G11C2211/5621 ,  G11C2211/5642

摘要： An error detection and data recovery operation for a non-volatile memory system. Even after a programming operation for a set of storage elements is successfully completed, the data of some storage elements may be corrupted. For example, erased state storage element may be disturbed by programming of other storage elements. To allow recovery of data in such situations, associated data latches can be configured to allow the erased state storage elements to be distinguished from other data states once programming is completed. Furthermore, a single read operation can be performed after programming is completed. Logical operations are performed using results from the read operation, and values in the data latches, to identify erased state storage elements which have strayed to another data state. If the number of errors exceeds a threshold, a full recovery operation is initiated in which read operations are performed for the remaining states.

摘要翻译： 用于非易失性存储器系统的错误检测和数据恢复操作。 即使在一组存储元件的编程操作成功完成之后，一些存储元件的数据也可能被破坏。 例如，擦除状态存储元件可能受到其他存储元件的编程的干扰。 为了允许在这种情况下恢复数据，相关联的数据锁存器可以被配置为允许擦除状态存储元件在编程完成之后与其他数据状态区分开来。 此外，可以在编程完成之后执行单个读取操作。 使用读取操作的结果和数据锁存器中的值执行逻辑运算，以识别已经偏移到另一数据状态的擦除状态存储元件。 如果错误数量超过阈值，则启动完全恢复操作，在其中执行剩余状态的读取操作。

公开(公告)号：US20120081963A1

公开(公告)日：2012-04-05

申请号：US12894889

申请日：2010-09-30

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Henry Chin

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Henry Chin

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C7/02 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： In a programming operation, selected storage elements which reach a lockout condition are subject to reduced channel boosting in a program portion of the next program-verify iteration, to reduce coupling effects on the storage elements which continue to be programmed. In subsequent program-verify iterations, the locked out storage elements are subject to full channel boosting. Or, the boosting can be stepped up over multiple program-verify iterations after lockout. The amount of channel boosting can be set by adjusting the timing of a channel pre-charge operation and by stepping up pass voltages which are applied to unselected word lines. The reduced channel boosting can be implemented for a range of program-verify iterations where the lockout condition is most likely to be first reached, for one or more target data states.

摘要翻译： 在编程操作中，达到锁定状态的所选择的存储元件在下一个程序验证迭代的程序部分中经历减少的信道增强，以减少对继续被编程的存储元件的耦合效应。 在随后的程序验证迭代中，锁定的存储元件进行全通道升压。 或者，在锁定之后，可以通过多次程序验证迭代来加强升压。 可以通过调整通道预充电操作的定时和通过加压施加到未选字线的通过电压来设置通道升压量。 对于一个或多个目标数据状态，减少的信道增强可以针对最可能首先达到锁定条件的一系列程序验证迭代来实现。

公开(公告)号：US20120182809A1

公开(公告)日：2012-07-19

申请号：US13428305

申请日：2012-03-23

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Grishma Shah

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Grishma Shah

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states.

摘要翻译： 在编程操作中，选择的字线上的所选择的存储元件被编程，同时通过通道增强来禁止所选字线上的未选择的存储元件的编程。 为了提供足够但不是过高的升压水平，可以基于未选择的存储元件的数据状态来设定升压量。 可以为代表较低阈值电压的较低数据状态提供更大量的升压，因此更易受编程干扰的影响。 一个共同的升压方案可以用于多个数据状态的组。 可以通过调整用于通道预充电操作的电压的时序和幅度以及施加到字线的通过电压来设置升压量。 在一种方法中，可以使用未选择字线上的阶梯式通过电压来调整具有所选数据状态的通道的升压。

公开(公告)号：US08130556B2

公开(公告)日：2012-03-06

申请号：US12398368

申请日：2009-03-05

申请人： Jeffrey W. Lutze ,  Deepanshu Dutta

发明人： Jeffrey W. Lutze ,  Deepanshu Dutta

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

摘要翻译： 编程技术通过使用选择的位线模式进行编程来减少一组非易失性存储元件中的编程干扰，这增加了禁止信道的钳位升压电位以避免编程干扰。 一个方面将交替的相邻位线对组合成第一和第二组。 双编程脉冲被施加到选定的字线。 第一组位线在第一脉冲期间被编程，并且第二组位线在第二脉冲期间被编程。 然后对所有位线执行验证操作。 当特定位线被禁止时，其相邻位线中的至少一个也将被禁止，使得特定位线的通道将被充分提升。 另一个方面分别编写每第三个位线。 修改的布局允许使用奇偶校验感测电路来感测相邻的位线对。

公开(公告)号：US20120014184A1

公开(公告)日：2012-01-19

申请号：US12838902

申请日：2010-07-19

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3454 ,  G11C16/3486 ,  G11C2216/14

摘要： Threshold voltage distributions in a non-volatile memory device are narrowed, and/or programming time is reduced, using a programming technique in which the bit line voltage for storage elements having a target data state is stepped up, in lock step with a step up in the program voltage. The step up in the bit line voltage is performed at different times in the programming pass, for different subsets of storage elements, according to their target data state. The start and stop of the step up in the bit line voltage can be set based on a fixed program pulse number, or adaptive based on a programming progress. Variations include using a fixed bit line step, a varying bit line step, a data state-dependent bit line step, an option to not step up the bit line for one or more data states and an option to add an additional bit line bias.

摘要翻译： 使用编程技术使非易失性存储器件中的阈值电压分布变窄，并且/或编程时间减少，其中具有目标数据状态的存储元件的位线电压被升高，在升压锁定步骤中 在编程电压。 根据其目标数据状态，针对存储元件的不同子集，在编程遍历中的不同时刻对位线电压进行升压。 可以基于固定的编程脉冲数或基于编程进度的自适应来设置位线电压中的升压的开始和停止。 变化包括使用固定的位线步长，变化的位线步长，数据状态相关的位线步长，不增加一个或多个数据状态的位线的选项以及增加额外位线偏置的选项。

公开(公告)号：US20110267888A1

公开(公告)日：2011-11-03

申请号：US13181750

申请日：2011-07-13

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/0483

摘要： A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage.

摘要翻译： 擦除非易失性存储器的技术将p阱电压施加到衬底并驱动选择栅极电压以精确地控制选择栅极电压以提高写入擦除耐久性。 NAND串的源极和漏极侧选择栅极被驱动，以优化耐久性。 在一种方法中，与p阱电压一致，在擦除操作期间以特定电平驱动选择栅极。

公开(公告)号：US20110182121A1

公开(公告)日：2011-07-28

申请号：US12695918

申请日：2010-01-28

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yan Li

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yan Li

IPC分类号： G11C16/06 ,  G11C7/10

CPC分类号： G11C11/5628 ,  G11C16/3418 ,  G11C29/00 ,  G11C2211/5621 ,  G11C2211/5642

摘要： An error detection and data recovery operation for a non-volatile memory system. Even after a programming operation for a set of storage elements is successfully completed, the data of some storage elements may be corrupted. For example, erased state storage element may be disturbed by programming of other storage elements. To allow recovery of data in such situations, associated data latches can be configured to allow the erased state storage elements to be distinguished from other data states once programming is completed. Furthermore, a single read operation can be performed after programming is completed. Logical operations are performed using results from the read operation, and values in the data latches, to identify erased state storage elements which have strayed to another data state. If the number of errors exceeds a threshold, a full recovery operation is initiated in which read operations are performed for the remaining states.

摘要翻译： 用于非易失性存储器系统的错误检测和数据恢复操作。 即使在一组存储元件的编程操作成功完成之后，一些存储元件的数据也可能被破坏。 例如，擦除状态存储元件可能受到其他存储元件的编程的干扰。 为了允许在这种情况下恢复数据，相关联的数据锁存器可以被配置为允许擦除状态存储元件在编程完成之后与其他数据状态区分开来。 此外，可以在编程完成之后执行单个读取操作。 使用读取操作的结果和数据锁存器中的值执行逻辑运算，以识别已经偏移到另一数据状态的擦除状态存储元件。 如果错误数量超过阈值，则启动完全恢复操作，在其中执行剩余状态的读取操作。

公开(公告)号：US07876611B2

公开(公告)日：2011-01-25

申请号：US12188629

申请日：2008-08-08

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3418

摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.

摘要翻译： 通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。 执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压 字线。 当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。 也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据 相邻存储元件。

公开(公告)号：US20100238730A1

公开(公告)日：2010-09-23

申请号：US12406014

申请日：2009-03-17

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/0483

摘要： A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives or floats select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates float after being driven at a specific initial level, to reach a specific, optimal final level. In another approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage. In another approach, onset of select gate floating is delayed while the p-well voltage ramps up. In another approach, p-well voltage is ramped up in two steps, and the select gates are not floated until the second ramp begins. Floating can be achieved by raising the drive voltage to cut off pass gates of the select gates.

摘要翻译： 擦除非易失性存储器的技术将p阱电压施加到衬底并且驱动或浮动选择栅极电压以精确地控制选择栅极电压以改善写入擦除耐久性。 NAND串的源极和漏极侧选择栅极被驱动，以优化耐久性。 在一种方法中，选择门在被特定初始级别驱动之后浮动，以达到特定的最佳最终级别。 在另一种方法中，与p阱电压一致，在擦除操作期间，选择栅极以特定电平驱动。 在另一种方法中，选择栅极浮动的开始被延迟，而p阱电压上升。 在另一种方法中，p阱电压以两个步骤升高，并且在第二个斜坡开始之前，选择栅极不浮动。 可以通过提高驱动电压来切断选通门的通孔来实现浮动。

公开(公告)号：US20100110792A1

公开(公告)日：2010-05-06

申请号：US12398368

申请日：2009-03-05

申请人： Jeffrey W. Lutze ,  Deepanshu Dutta

发明人： Jeffrey W. Lutze ,  Deepanshu Dutta

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

摘要翻译： 编程技术通过使用选择的位线模式进行编程来减少一组非易失性存储元件中的编程干扰，这增加了禁止信道的钳位升压电位以避免编程干扰。 一个方面将交替的相邻位线对组合成第一和第二组。 双编程脉冲被施加到选定的字线。 第一组位线在第一脉冲期间被编程，并且第二组位线在第二脉冲期间被编程。 然后对所有位线执行验证操作。 当特定位线被禁止时，其相邻位线中的至少一个也将被禁止，使得特定位线的通道将被充分提升。 另一个方面分别编写每第三个位线。 修改的布局允许使用奇偶校验感测电路来感测相邻的位线对。