发明申请
US20100117705A1 Semiconductor integrated circuit device having plural delay paths and controller capable of Blocking signal transmission in delay path
失效
具有多个延迟路径的半导体集成电路装置和能够阻止延迟路径中的信号传输的控制器
- 专利标题： Semiconductor integrated circuit device having plural delay paths and controller capable of Blocking signal transmission in delay path
- 专利标题（中）： 具有多个延迟路径的半导体集成电路装置和能够阻止延迟路径中的信号传输的控制器
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申请号： US12588993申请日： 2009-11-04
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公开(公告)号： US20100117705A1公开(公告)日： 2010-05-13
- 发明人: Masahiro Nomura
- 申请人： Masahiro Nomura
- 申请人地址： JP Kawasaki
- 专利权人： NEC ELECTRONICS CORPORATION
- 当前专利权人： NEC ELECTRONICS CORPORATION
- 当前专利权人地址： JP Kawasaki
- 优先权： JP2008-288846 20081111
- 主分类号： H03H11/26
- IPC分类号： H03H11/26
摘要：
A plurality of delay paths are connected in parallel between two synchronous operation circuits operating in synchronism with a clock signal CLK, and enable transmission of a signal. A delay detection unit detects the respective delay times of the plurality of delay paths, and a control unit selects one delay path from among the plurality of delay paths based on the detection results from the delay detection unit, and controls the blocking of signal transmission in the delay paths other than the selected one delay path.