发明申请
- 专利标题： REFERENCE VOLTAGE GENERATION CIRCUIT AND BIAS CIRCUIT
- 专利标题（中）： 参考电压发生电路和偏置电路
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申请号： US12417730申请日： 2009-04-03
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公开(公告)号： US20100127689A1公开(公告)日： 2010-05-27
- 发明人: Kazuya Yamamoto , Miyo Miyashita
- 申请人： Kazuya Yamamoto , Miyo Miyashita
- 申请人地址： JP Tokyo
- 专利权人： MITSUBISHI ELECTRIC CORPORATION
- 当前专利权人： MITSUBISHI ELECTRIC CORPORATION
- 当前专利权人地址： JP Tokyo
- 优先权： JP2008-298431 20081121
- 主分类号： G05F3/16
- IPC分类号： G05F3/16 ; G05F1/10
摘要：
A reference voltage generation circuit comprises: a first depletion mode FET; a second depletion mode FET; a first resistor; a first bipolar transistor; a second resistor; a second bipolar transistor; a third bipolar transistor; a third resistor; a third depletion mode FET having its drain connected to a second end of the first resistor and to the collector of the first bipolar transistor; and a fourth bipolar transistor having its base and collector connected to the gate and the source of the third depletion mode FET, and its emitter grounded, wherein source voltage of the second depletion mode FET is output as a reference voltage.
公开/授权文献
- US08049483B2 Reference voltage generation circuit and bias circuit 公开/授权日：2011-11-01
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