发明申请
US20100138608A1 Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor
有权
用于处理器的微操作缓存中的管道包含和指令重新启动的方法和装置
- 专利标题: Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor
- 专利标题(中): 用于处理器的微操作缓存中的管道包含和指令重新启动的方法和装置
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申请号: US12317959申请日: 2008-12-31
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公开(公告)号: US20100138608A1公开(公告)日: 2010-06-03
- 发明人: Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ilhyun Kim , Ron Gabor , Lior Libis , Gregory Pribush
- 申请人: Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ilhyun Kim , Ron Gabor , Lior Libis , Gregory Pribush
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.