发明申请
US20100156460A1 (N+1) INPUT FLIP-FLOP PACKING WITH LOGIC IN FPGA ARCHITECTURES
有权
（N + 1）在FPGA架构中使用逻辑输入FLOP-FLOP包装
- 专利标题： (N+1) INPUT FLIP-FLOP PACKING WITH LOGIC IN FPGA ARCHITECTURES
- 专利标题（中）： （N + 1）在FPGA架构中使用逻辑输入FLOP-FLOP包装
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申请号： US12717315申请日： 2010-03-04
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公开(公告)号： US20100156460A1公开(公告)日： 2010-06-24
- 发明人: Sinan Kaptanoglu
- 申请人： Sinan Kaptanoglu
- 专利权人： Actel Corporation
- 当前专利权人： Actel Corporation
- 主分类号： H03K19/177
- IPC分类号： H03K19/177
摘要：
A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.
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