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    (N+1) input flip-flop packing with logic in FPGA architectures
    2.
    发明授权
    (N+1) input flip-flop packing with logic in FPGA architectures 有权
    （N + 1）输入触发器封装，具有FPGA架构中的逻辑

    公开(公告)号：US07944238B2

    公开(公告)日：2011-05-17

    申请号：US12717315

    申请日：2010-03-04

    申请人： Sinan Kaptanoglu

    发明人： Sinan Kaptanoglu

    IPC分类号： G06F7/38 ,  H03K19/177

    CPC分类号： H03K19/1737 ,  H03K19/17728

    摘要： A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.

    摘要翻译： 逻辑模块和触发器包括具有耦合到路由资源的数据输入的输入多路复用器。 时钟复用器具有耦合到时钟资源的输入和输出。 输入选择多路复用器具有耦合到输入多路复用器的输出的第一输入。 触发器具有耦合到时钟复用器的输出的时钟输入和耦合到输入选择多路复用器的输入的数据输出。 逻辑模块具有耦合到输入选择多路复用器的输出的数据输入。 触发器多路复用器耦合到触发器的数据输入，并具有耦合到第一输入多路复用器的输出，逻辑模块的数据输出和耦合到路由资源的第三输入的输入输入。

    Field programmable gate array architecture having Clos network-based input interconnect
    3.
    发明授权
    Field programmable gate array architecture having Clos network-based input interconnect 有权
    具有基于Clos网络的输入互连的现场可编程门阵列结构

    公开(公告)号：US07924052B1

    公开(公告)日：2011-04-12

    申请号：US12361835

    申请日：2009-01-29

    申请人： Wenyi Feng ,  Jonathan Greene ,  Sinan Kaptanoglu

    发明人： Wenyi Feng ,  Jonathan Greene ,  Sinan Kaptanoglu

    IPC分类号： H01L25/00

    CPC分类号： H03K19/17736

    摘要： A cluster internal routing network for use in a programmable logic device with a cluster-based architecture employs a Clos network-based routing architecture. The routing architecture is a multi-stage blocking architecture, where the number of inputs to the first stage exceeds the number of outputs from the first stage.

    摘要翻译： 在具有基于群集的架构的可编程逻辑设备中使用的集群内部路由网络采用基于Clos网络的路由架构。 路由架构是多级阻塞架构，其中第一级的输入数量超过了第一级的输出数量。

    Fracturable incomplete look up table area efficient logic elements
    5.
    发明授权
    Fracturable incomplete look up table area efficient logic elements 失效
    不可靠的查找表区域有效的逻辑元素

    公开(公告)号：US07030650B1

    公开(公告)日：2006-04-18

    申请号：US10985574

    申请日：2004-11-10

    申请人： Sinan Kaptanoglu ,  David Lewis ,  Bruce Pedersen

    发明人： Sinan Kaptanoglu ,  David Lewis ,  Bruce Pedersen

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17748 ,  H03K19/17728

    摘要： Disclosed is a configurable logic circuit that includes at least 6 inputs and at least two outputs. The configurable logic element can carry out only a subset of all 6-input logic functions and, thus, requires a substantially smaller silicon area than a 6-LUT that can perform all 6-input logic functions. Also, the configurable logic circuit can be configured such that a first subset of the inputs drive one of the outputs and a second subset of the inputs drive another output.

    摘要翻译： 公开了一种可配置逻辑电路，其包括至少6个输入和至少两个输出。 可配置逻辑元件只能执行所有6输入逻辑功能的一个子集，因此需要比可执行所有6输入逻辑功能的6-LUT更小的硅面积。 而且，可配置逻辑电路可被配置为使得输入的第一子集驱动输出之一，并且输入的第二子集驱动另一输出。

    Block level routing architecture in a field programmable gate array
    6.
    发明申请
    Block level routing architecture in a field programmable gate array 失效
    块级路由架构在现场可编程门阵列中

    公开(公告)号：US20050184753A1

    公开(公告)日：2005-08-25

    申请号：US11088621

    申请日：2005-03-23

    申请人： Sinan Kaptanoglu

    发明人： Sinan Kaptanoglu

    IPC分类号： H01L27/118 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  H01L27/11803

    摘要： An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors. Each BC routing channel is coupled to an expressway tab to provide access for each B1 block to the expressway routing channels M1, M2, and M3, respectively. Each BC routing channel has nine interconnect conductors which are grouped into three groups of three interconnect conductors. Each group of three interconnect conductors is connected to a first side of a Extension Block (EB) 3×3 switch matrix. A second side of each EB 3×3 switch matrix is coupled to the E-tab. Between adjacent B1 blocks , in both the horizontal and vertical directions, the leads on the second side of a first EB 3×3 switch matrix may be coupled to the leads on the second side of second EB3×3 switch matrix by BC criss-cross extension.

    摘要翻译： FPGA架构具有顶级，中级和低级。 该体系结构的顶层是排列成矩形阵列并由外围的I / O块包围的B16x16瓦数组。 在B16x16瓦片的四面中，每个I / O块也与高速公路路由通道相关联。 中层层次的B16x16瓦片是16块16块阵列。 中间级别的路由资源是包括互连导体组的高速公路路由信道M 1，M 2和M 3。 在半层次FPGA架构的最底层，有块连接（BC）路由通道，局域网（LM）路由通道和直接连接（DC）互连导线。 每个BC路由信道被耦合到高速公路标签，以分别向高速公路路由信道M 1，M 2和M 3提供每个B1块的接入。 每个BC路由信道具有九个互连导体，它们分成三组三个互连导体。 每组三个互连导体连接到扩展块（EB）3x3开关矩阵的第一侧。 每个EB 3x3开关矩阵的第二面耦合到E-tab。 在相邻B1块之间，在水平和垂直方向上，第一EB 3×3开关矩阵的第二侧上的引线可以通过BC交叉扩展耦合到第二EB3×3开关矩阵的第二侧上的引线。

    Turn architecture for routing resources in a field programmable gate array
    7.
    发明授权
    Turn architecture for routing resources in a field programmable gate array 有权

    公开(公告)号：US06934927B2

    公开(公告)日：2005-08-23

    申请号：US10429003

    申请日：2003-04-30

    申请人： Sinan Kaptanoglu

    发明人： Sinan Kaptanoglu

    IPC分类号： G06F17/50 ,  H03K17/693 ,  H03K19/177 ,  H01L25/00

    CPC分类号： H03K19/17736 ,  H03K19/17796

    摘要： An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The B16×16 tile is a nesting of a B2×2 tile that includes a two by two array of four B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. The expressway routing channels M1, M2, and M3 are segmented, and between each of the segments in the expressway routing channels M1, M2, and M3 are disposed extensions that can extend the expressway routing channel M1, M2, or M3 an identical distance along the same direction. The expressway routing channels M1, M2, and M3 run both vertically through every column and horizontally through every row of B2×2 tiles. At the intersections of each of the expressway routing channels M1, M2, and M3 in the horizontal direction with the expressway routing channels M1, M2 and M3 in the vertical direction is an expressway turn (E-turn) disposed at the center of each B2×2 tile. An E-turn is a passive device that includes a matrix of reprogrammable switches. The reprogrammable switches are preferably a pass device controlled by an SRAM bit. The interconnect conductors in the expressway routing channels M1, M2 and M3 that are fed into an E-turn may be coupled to many of the other interconnect conductors in the expressway routing channels M1, M2 and M3 that come into the E-turn by the programmable switches. Further, the interconnect conductors in the expressway routing channels M1, M2 and M3 that are fed into an E-turn continue in the same direction through the E-turn, even though the interconnect conductors are coupled to other interconnect conductors by the reprogrammable switches.

    Block symmetrization in a field programmable gate array
    8.
    发明授权
    Block symmetrization in a field programmable gate array 有权
    在现场可编程门阵列中的块对称

    公开(公告)号：US06861869B1

    公开(公告)日：2005-03-01

    申请号：US10670883

    申请日：2003-09-24

    申请人： Sinan Kaptanoglu

    发明人： Sinan Kaptanoglu

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17728

    摘要： A architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have three inputs and one output. Each of the LUT2s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUTs are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.

    摘要翻译： 一个建筑有顶级，中级和低级。 顶级是由I / O块包围的B16x16瓦数组。 中间路由资源是高速公路路由信道，包括互连导体。 在最底层，有块连接路由通道，本地网状路由通道和直接连接互连导体，以将逻辑元件连接到更多的路由资源。 每个B1块包括四组设备。 每个簇包括第一和第二LUT3，LUT2和DFF。 每个LUT3有三个输入和一个输出。 每个LUT2有两个输入和一个输出。 每个DFF都有数据输入和数据输出。 在每个簇中，LUT的输出被复用到DFF的输入，并且与DFF的输出对称，以形成每个簇的两个输出。

    Block symmetrization in a field programmable gate array
    9.
    发明授权
    Block symmetrization in a field programmable gate array 有权
    在现场可编程门阵列中的块对称

    公开(公告)号：US06680624B2

    公开(公告)日：2004-01-20

    申请号：US09880629

    申请日：2001-06-12

    申请人： Sinan Kaptanoglu

    发明人： Sinan Kaptanoglu

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/17796

    摘要： An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the four clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have first, second, and third inputs and a single output. Each of the LUT2s have first and second inputs and a single output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are muliplexed to the input of DFF, and symmetrized with the output of the DFF to form first and second outputs of each of the clusters.

    摘要翻译： FPGA架构具有顶级，中级和低级。 该体系结构的顶层是排列成矩形阵列并由外围的I / O块包围的B16x16瓦数组。 在B16x16瓦片的四面中，每个I / O块也与高速公路路由通道相关联。 中层层次的B16x16瓦片是16块16块阵列。 中间层次的路由资源是包括互连导体组的高速公路路由信道M1，M2和M3。 在半层次FPGA架构的最底层，存在块连接（BC）路由通道，局域网（LM）路由通道和直接连接（DC）互连导体，以将逻辑元件连接到更多的路由资源。 每个B1块包括四组设备。 四个群集中的每一个包括第一和第二LUT3，LUT2和DFF。 每个LUT3具有第一，第二和第三输入和单个输出。 每个LUT2具有第一和第二输入和单个输出。 每个DFF都有数据输入和数据输出。 在每个簇中，LUT3的输出与DFF的输入混合，并且与DFF的输出对称，以形成每个簇的第一和第二输出。

    Flexible FPGA input/output architecture
    10.
    发明授权
    Flexible FPGA input/output architecture 失效
    灵活的FPGA输入/输出架构

    公开(公告)号：US5625301A

    公开(公告)日：1997-04-29

    申请号：US444243

    申请日：1995-05-18

    申请人： William C. Plants ,  Sinan Kaptanoglu ,  Jung-Cheun Lien ,  King W. Chan ,  Khaled A. El-Ayat

    发明人： William C. Plants ,  Sinan Kaptanoglu ,  Jung-Cheun Lien ,  King W. Chan ,  Khaled A. El-Ayat

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17744 ,  H03K19/17704

    摘要： An input/output architecture for a field-programmable gate array integrated circuit including a plurality of logic function modules in an array of rows and columns, each of the modules having at least one input conductor and at least one output conductor; a plurality of interconnect conductors, comprising a plurality of input/output pads; a plurality of input/output kernels, each input/output kernel comprising an input buffer having a data input connected to one of the I/O pads and a data output connected to an input buffer data conductor, an output buffer having a data input connected to an output buffer data conductor, a data output connected to the I/O pad, and an enable input connected to an output buffer enable conductor; the input buffer data conductors extending in either the row or the column direction, different ones of the input buffer data conductors extending different numbers of rows or columns, the input buffer data conductors forming first intersections with inputs of the modules; the output buffer data conductors and output buffer enable conductors extending in either the row or the column direction, different ones of the output buffer data conductors and output buffer enable conductors extending different numbers of rows or columns, the input buffer data conductors forming second intersections with outputs of the modules; and user-programmable interconnect elements connected across selected ones of the first and second intersections.

    摘要翻译： 一种用于现场可编程门阵列集成电路的输入/输出架构，包括行和列阵列中的多个逻辑功能模块，每个模块具有至少一个输入导体和至少一个输出导体; 多个互连导体，包括多个输入/输出焊盘; 多个输入/输出内核，每个输入/输出内核包括输入缓冲器，该输入缓冲器具有连接到I / O焊盘之一的数据输入和连接到输入缓冲器数据导体的数据输出;输出缓冲器，其具有连接的数据输入 连接到输出缓冲器数据导体，连接到I / O焊盘的数据输出和连接到输出缓冲器使能导体的使能输入; 输入缓冲器数据导体在行或列方向上延伸，不同的输入缓冲器数据导体延伸不同数量的行或列，输入缓冲器数据导体与模块的输入形成第一交点; 输出缓冲器数据导体和输出缓冲器使能导体在行或列方向上延伸，不同的输出缓冲器数据导体和输出缓冲器使能导体延伸不同数量的行或列，输入缓冲器数据导体与第 模块输出; 以及连接在第一和第二交叉点中的选定的互连元件之间的用户可编程互连元件。