A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.