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公开(公告)号：US20100165754A1
公开(公告)日：2010-07-01
申请号：US12646827
申请日：2009-12-23
CPC分类号： G11C7/22 , G11C7/08 , G11C11/413
摘要： A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.
摘要翻译： 一种用于改善穿过多个电压域的多个信号路径中的信号同步的系统和方法。 根据本公开的实施例，存储器装置优选用于信号同步。 所有读/写和时钟信号和其他控制信号被驱动到周边电源（Vp）电平，除了以核心电源（Vc）电平驱动的字线（WL [i]）信号。 通过这样做，与核心供应（Vc）相关的较低的平均和峰值电流消耗是通过恒定的延迟实现的，并且在穿过多个电压域的信号路径中保持所需的信号同步。
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公开(公告)号：US08693267B2
公开(公告)日：2014-04-08
申请号：US12646827
申请日：2009-12-23
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/08 , G11C11/413
摘要： A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.
摘要翻译： 一种用于改善穿过多个电压域的多个信号路径中的信号同步的系统和方法。 根据本公开的实施例，存储器装置优选用于信号同步。 所有读/写和时钟信号和其他控制信号被驱动到周边电源（Vp）电平，除了以核心电源（Vc）电平驱动的字线（WL [i]）信号。 通过这样做，与核心供应（Vc）相关的较低的平均和峰值电流消耗是通过恒定的延迟实现的，并且在穿过多个电压域的信号路径中保持所需的信号同步。
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公开(公告)号：US20130170275A1
公开(公告)日：2013-07-04
申请号：US13591663
申请日：2012-08-22
申请人： Shishir Kumar , Dibya Dipti , Pierre Malinge
发明人： Shishir Kumar , Dibya Dipti , Pierre Malinge
IPC分类号： G11C5/06
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207 , H01L27/11
摘要： A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active are that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that form the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.
摘要翻译： 双端口SRAM有两个数据存储节点，一个真实的数据和补充数据。 第一下拉晶体管具有形成第一晶体管的漏极区域和与存储器单元的所有其它晶体管有源区域物理隔离的真实数据存储节点的有源。 第二下拉晶体管具有形成第二晶体管的漏极区域的有源区域，该第二晶体管是与存储器单元的所有其它晶体管有源区域物理隔离的互补数据节点。
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公开(公告)号：US09006841B2
公开(公告)日：2015-04-14
申请号：US13591663
申请日：2012-08-22
申请人： Shishir Kumar , Dibya Dipti , Pierre Malinge
发明人： Shishir Kumar , Dibya Dipti , Pierre Malinge
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207 , H01L27/11
摘要： A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active area that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that forms the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.
摘要翻译： 双端口SRAM有两个数据存储节点，一个真实的数据和补充数据。 第一下拉晶体管具有形成第一晶体管的漏极区域和与存储器单元的所有其它晶体管有源区域物理隔离的真实数据存储节点的有源区域。 第二下拉晶体管具有形成第二晶体管的漏极区域的有源区域，该第二晶体管是与存储器单元的所有其它晶体管有源区域物理隔离的互补数据节点。
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