Invention Application
- Patent Title: REDUCING WARPAGE FOR FAN-OUT WAFER LEVEL PACKAGING
- Patent Title (中): 降低风扇水平包装的起伏
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Application No.: US12495734Application Date: 2009-06-30
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Publication No.: US20100167471A1Publication Date: 2010-07-01
- Inventor: Yonggang Jin , Xavier Baraton , Faxing Che
- Applicant: Yonggang Jin , Xavier Baraton , Faxing Che
- Applicant Address: SG Singapore
- Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
- Current Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L21/60

Abstract:
Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.
Information query
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