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公开(公告)号：US20130001795A1
公开(公告)日：2013-01-03
申请号：US13407295
申请日：2012-02-28
Applicant: Teck Guan LIM , Ying Ying Lim , Yee Mong Khoo , Navas Khan Oratti Kalandar , Faxing Che , Ser Choong Chong , Soon Wee David Ho , Shan Gao , Rui Li
Inventor： Teck Guan LIM , Ying Ying Lim , Yee Mong Khoo , Navas Khan Oratti Kalandar , Faxing Che , Ser Choong Chong , Soon Wee David Ho , Shan Gao , Rui Li
IPC: H01L23/48
CPC classification number: H01L24/96 , H01L23/3107 , H01L23/481 , H01L24/05 , H01L24/13 , H01L2223/6677 , H01L2224/02372 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/96 , H01L2924/10253 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/1306 , H01L2924/181 , H01L2224/03 , H01L2224/11 , H01L2924/014 , H01L2924/00
Abstract: A wafer level package is provided. The wafer level package includes at least one chip with at least one electronic component, and at least one connecting chip with at least one through-silicon via, wherein the at least one through-silicon via is electrically coupled to the at least one chip. Further embodiments relate to a method of forming the wafer level package.
Abstract translation: 提供晶圆级封装。 晶片级封装包括具有至少一个电子部件的至少一个芯片和至少一个具有至少一个穿硅通孔的连接芯片，其中所述至少一个穿硅通孔电耦合到所述至少一个芯片。 另外的实施例涉及形成晶片级封装的方法。
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公开(公告)号：US20100167471A1
公开(公告)日：2010-07-01
申请号：US12495734
申请日：2009-06-30
Applicant: Yonggang Jin , Xavier Baraton , Faxing Che
Inventor： Yonggang Jin , Xavier Baraton , Faxing Che
CPC classification number: H01L23/3128 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2224/82 , H01L2924/00
Abstract: Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.
Abstract translation: 扇出晶片级封装包括具有顶表面，底表面，多个侧表面以及限定在顶表面上的接合焊盘的集成电路。 密封剂层基本上围绕集成电路的侧表面，密封剂层的高度基本上等于集成电路的高度。 凸块与集成电路间隔开，并且再分配层将集成电路的接合焊盘电耦合到凸块。
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公开(公告)号：US09012269B2
公开(公告)日：2015-04-21
申请号：US13488276
申请日：2012-06-04
Applicant: Yonggang Jin , Xavier Baraton , Faxing Che
Inventor： Yonggang Jin , Xavier Baraton , Faxing Che
IPC: H01L21/56 , H01L23/31 , H01L23/538 , H01L23/00
CPC classification number: H01L23/3128 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2224/82 , H01L2924/00
Abstract: Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.
Abstract translation: 扇出晶片级封装包括具有顶表面，底表面，多个侧表面以及限定在顶表面上的接合焊盘的集成电路。 密封剂层基本上围绕集成电路的侧表面，密封剂层的高度基本上等于集成电路的高度。 凸块与集成电路间隔开，并且再分配层将集成电路的接合焊盘电耦合到凸块。
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公开(公告)号：US20120244664A1
公开(公告)日：2012-09-27
申请号：US13488276
申请日：2012-06-04
Applicant: Yonggang Jin , Xavier Baraton , Faxing Che
Inventor： Yonggang Jin , Xavier Baraton , Faxing Che
IPC: H01L21/56
CPC classification number: H01L23/3128 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2224/82 , H01L2924/00
Abstract: Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.
Abstract translation: 扇出晶片级封装包括具有顶表面，底表面，多个侧表面以及限定在顶表面上的接合焊盘的集成电路。 密封剂层基本上围绕集成电路的侧表面，密封剂层的高度基本上等于集成电路的高度。 凸块与集成电路间隔开，并且再分配层将集成电路的接合焊盘电耦合到凸块。
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