发明申请
US20100167484A1 Gate line edge roughness reduction by using 2P/2E process together with high temperature bake
有权
通过使用2P / 2E工艺与高温烘烤进行栅极边缘粗糙度降低
- 专利标题： Gate line edge roughness reduction by using 2P/2E process together with high temperature bake
- 专利标题（中）： 通过使用2P / 2E工艺与高温烘烤进行栅极边缘粗糙度降低
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申请号： US12648802申请日： 2009-12-29
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公开(公告)号： US20100167484A1公开(公告)日： 2010-07-01
- 发明人: Yiming Gu , James Walter Blatchford
- 申请人： Yiming Gu , James Walter Blatchford
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 主分类号： H01L21/8234
- IPC分类号： H01L21/8234 ; H01L21/28 ; H01L21/3205 ; G03F7/20
摘要：
A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.
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