发明申请
US20100169727A1 EDA TOOL, SEMICONDUCTOR DEVICE, AND SCAN CHAIN CONFIGURATION METHOD
审中-公开
EDA工具,半导体器件和扫描链配置方法
- 专利标题: EDA TOOL, SEMICONDUCTOR DEVICE, AND SCAN CHAIN CONFIGURATION METHOD
- 专利标题(中): EDA工具,半导体器件和扫描链配置方法
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申请号: US12647475申请日: 2009-12-26
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公开(公告)号: US20100169727A1公开(公告)日: 2010-07-01
- 发明人: Daisuke ITO , Hiroki Yamanaka , Koki Tsutsumida
- 申请人: Daisuke ITO , Hiroki Yamanaka , Koki Tsutsumida
- 专利权人: RENESAS TECHNOLOGY CORP.
- 当前专利权人: RENESAS TECHNOLOGY CORP.
- 优先权: JP2008-333335 20081226
- 主分类号: G01R31/3177
- IPC分类号: G01R31/3177 ; G06F11/25
摘要:
There is provided a technique for avoiding test-time IR drops which occur when the frequency that adjacent FFs in a scan chain have different logical values increases. An expected value derivation module derives the expected value of each FF by calculating probability propagation or performing logic simulation. A grouping module groups each FF subject to a test into a number of groups by referring to the obtained expected value. A scan chain configuration module pairs two groups whose logical-value-1 intake frequencies are opposite to each other, performs logic reversal on one group, and configures one scan chain.
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