发明申请
US20100169727A1 EDA TOOL, SEMICONDUCTOR DEVICE, AND SCAN CHAIN CONFIGURATION METHOD 审中-公开
EDA工具,半导体器件和扫描链配置方法

EDA TOOL, SEMICONDUCTOR DEVICE, AND SCAN CHAIN CONFIGURATION METHOD
摘要:
There is provided a technique for avoiding test-time IR drops which occur when the frequency that adjacent FFs in a scan chain have different logical values increases. An expected value derivation module derives the expected value of each FF by calculating probability propagation or performing logic simulation. A grouping module groups each FF subject to a test into a number of groups by referring to the obtained expected value. A scan chain configuration module pairs two groups whose logical-value-1 intake frequencies are opposite to each other, performs logic reversal on one group, and configures one scan chain.
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