EDA TOOL, SEMICONDUCTOR DEVICE, AND SCAN CHAIN CONFIGURATION METHOD
    1.
    发明申请
    EDA TOOL, SEMICONDUCTOR DEVICE, AND SCAN CHAIN CONFIGURATION METHOD 审中-公开
    EDA工具,半导体器件和扫描链配置方法

    公开(公告)号:US20100169727A1

    公开(公告)日:2010-07-01

    申请号:US12647475

    申请日:2009-12-26

    IPC分类号: G01R31/3177 G06F11/25

    CPC分类号: G01R31/318591

    摘要: There is provided a technique for avoiding test-time IR drops which occur when the frequency that adjacent FFs in a scan chain have different logical values increases. An expected value derivation module derives the expected value of each FF by calculating probability propagation or performing logic simulation. A grouping module groups each FF subject to a test into a number of groups by referring to the obtained expected value. A scan chain configuration module pairs two groups whose logical-value-1 intake frequencies are opposite to each other, performs logic reversal on one group, and configures one scan chain.

    摘要翻译: 提供了一种用于避免当扫描链中相邻的FF具有不同的逻辑值增加的频率时出现的测试时间IR下降的技术。 期望值推导模块通过计算概率传播或执行逻辑模拟得出每个FF的期望值。 分组模块通过参考获得的预期值将每个受试验的FF组合成多个组。 扫描链配置模块将逻辑1的进气频率彼此相反的两组对齐,在一组上执行逻辑反转,并配置一个扫描链。

    DELAY FAULT DIAGNOSIS PROGRAM
    2.
    发明申请
    DELAY FAULT DIAGNOSIS PROGRAM 失效
    延迟故障诊断程序

    公开(公告)号:US20100269003A1

    公开(公告)日:2010-10-21

    申请号:US12761335

    申请日:2010-04-15

    IPC分类号: G01R31/3177 G06F11/25

    CPC分类号: G01R31/318328

    摘要: An extraction unit of fault assumption and a finish-point FF is provided, the fault assumption is selected from fault assumption information, and a logic trace is executed from the fault assumption toward an output side. A test result of a finish-point FF obtained as a result of the trace from the fault assumption is determined. The maximum value and the minimum value of the propagation route up to the finish-point FF are determined, and a delay margin is determined from the values. A delay range is determined by using the delay margin and the test result, and a fault candidate and a delay range of the delay fault are specified by the process of the determination of the fault candidate and the delay range.

    摘要翻译: 提供故障假设提取单元和终点FF,从故障假设信息中选择故障假设,从故障假设向输出侧执行逻辑跟踪。 确定作为从故障假设的轨迹的结果获得的终点FF的测试结果。 确定直到完成点FF的传播路径的最大值和最小值,并根据该值确定延迟余量。 通过使用延迟余量和测试结果确定延迟范围,通过确定故障候选和延迟范围的过程来指定延迟故障的故障候选和延迟范围。

    Delay fault diagnosis program
    3.
    发明授权
    Delay fault diagnosis program 失效
    延迟故障诊断程序

    公开(公告)号:US08392776B2

    公开(公告)日:2013-03-05

    申请号:US12761335

    申请日:2010-04-15

    IPC分类号: G01R31/28

    CPC分类号: G01R31/318328

    摘要: An extraction unit of fault assumption and a finish-point FF is provided, the fault assumption is selected from fault assumption information, and a logic trace is executed from the fault assumption toward an output side. A test result of a finish-point FF obtained as a result of the trace from the fault assumption is determined. The maximum value and the minimum value of the propagation route up to the finish-point FF are determined, and a delay margin is determined from the values. A delay range is determined by using the delay margin and the test result, and a fault candidate and a delay range of the delay fault are specified by the process of the determination of the fault candidate and the delay range.

    摘要翻译: 提供故障假设提取单元和终点FF,从故障假设信息中选择故障假设,从故障假设向输出侧执行逻辑跟踪。 确定作为从故障假设的轨迹的结果获得的终点FF的测试结果。 确定直到完成点FF的传播路径的最大值和最小值,并根据该值确定延迟余量。 通过使用延迟余量和测试结果确定延迟范围,通过确定故障候选和延迟范围的过程来指定延迟故障的故障候选和延迟范围。