发明申请
- 专利标题: METHOD AND APPARATUS FOR HARDWARE XML ACCELERATION
- 专利标题(中): 硬件XML加速的方法和装置
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申请号: US12730869申请日: 2010-03-24
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公开(公告)号: US20100180195A1公开(公告)日: 2010-07-15
- 发明人: Jochen Behrens , Marcelino M. Dignum , Wayne F. Seltzer , William T. Zaumen , John P. Petry , Santiago M. Pericas-Geertsen , Biswadeep Nag
- 申请人: Jochen Behrens , Marcelino M. Dignum , Wayne F. Seltzer , William T. Zaumen , John P. Petry , Santiago M. Pericas-Geertsen , Biswadeep Nag
- 申请人地址: US CA Redwood Shores
- 专利权人: ORACLE INTERNATIONAL CORPORATION
- 当前专利权人: ORACLE INTERNATIONAL CORPORATION
- 当前专利权人地址: US CA Redwood Shores
- 主分类号: G06F17/00
- IPC分类号: G06F17/00
摘要:
A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g., memory, bus) are greatly reduced, thereby providing significantly improved XML processing and security processing throughput.
公开/授权文献
- US08392824B2 Method and apparatus for hardware XML acceleration 公开/授权日:2013-03-05