发明申请
US20100190319A1 METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER
有权
使用耦合层形成包含自对准金属纳米线的浮动栅的存储器的方法
- 专利标题: METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER
- 专利标题(中): 使用耦合层形成包含自对准金属纳米线的浮动栅的存储器的方法
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申请号: US12754408申请日: 2010-04-05
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公开(公告)号: US20100190319A1公开(公告)日: 2010-07-29
- 发明人: Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
- 申请人: Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
- 主分类号: H01L21/28
- IPC分类号: H01L21/28
摘要:
Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
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