发明申请
US20100200920A1 Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection
有权
门极漏极(GD)钳位和ESD保护电路的配置用于电源器件击穿保护
- 专利标题: Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection
- 专利标题(中): 门极漏极(GD)钳位和ESD保护电路的配置用于电源器件击穿保护
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申请号: US12378039申请日: 2009-02-09
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公开(公告)号: US20100200920A1公开(公告)日: 2010-08-12
- 发明人: Yi Su , Anup Bhalla , Daniel Ng
- 申请人: Yi Su , Anup Bhalla , Daniel Ng
- 专利权人: Alpha & Omega Semiconductor, Inc.
- 当前专利权人: Alpha & Omega Semiconductor, Inc.
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.
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