发明申请
US20100200920A1 Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection 有权
门极漏极(GD)钳位和ESD保护电路的配置用于电源器件击穿保护

Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection
摘要:
A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.
信息查询
0/0