Invention Application
- Patent Title: SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING THE SAME
- Patent Title (中): 半导体存储器件及其读取方法
-
Application No.: US12706306Application Date: 2010-02-16
-
Publication No.: US20100208519A1Publication Date: 2010-08-19
- Inventor: Hitoshi SHIGA , Osamu Nagao
- Applicant: Hitoshi SHIGA , Osamu Nagao
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Priority: JP2009-036479 20090219
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
First and second data retaining circuits retain data read from memory cell and threshold voltage information indicating where in one of plural threshold voltage distributions threshold voltage of memory cell is located. Calculation device executes calculations among data retained in first and second data retaining circuit and data read by sense amplifier.Control circuit executes first operation of reading data from adjoining memory cell connected to second word line adjoining first word line connected to selected memory cell and retaining the data in first data retaining circuit, and second operation of changing respective word line voltages applied to first word line for reading data or threshold voltage information among plural values and selecting one of plural data read out by the plural values based on data retained in first data retaining circuit. Third operation of externally outputting selected data is executed simultaneously with one of successive first and second operations.
Information query