公开(公告)号：US08320187B2

公开(公告)日：2012-11-27

申请号：US13234628

申请日：2011-09-16

申请人： Osamu Nagao

发明人： Osamu Nagao

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C11/5607 ,  G11C11/5614 ,  G11C11/5642 ,  G11C11/5664 ,  G11C11/5671 ,  G11C11/5678 ,  G11C11/5685 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621

摘要： According to one embodiment, a nonvolatile semiconductor memory includes memory cells storing data of multi-level, a bit scan circuit to scan the number of to-be-written memory cells and the number of memory cells that have passed the verify, a processing unit to perform an operation process based on a scan result of the bit scan circuit, and a control circuit to control an operation of writing data according to a first mode in which a voltage used for an upper-data writing is calculated during a lower-data writing and a second mode used a voltage based on setting information. The bit scan circuit scans the number of to-be-written memory cells before starting writing and the processing unit compares the number of to-be-written memory cells with a criterion and determines one of the first and second modes for the writing based on a result of comparison.

摘要翻译： 根据一个实施例，非易失性半导体存储器包括存储多电平数据的存储单元，扫描待写入存储器单元的数量的位扫描电路和通过验证的存储单元的数量;处理单元 基于比特扫描电路的扫描结果执行操作处理，以及控制电路，用于根据第一模式控制写入数据的操作，其中在较低数据期间计算用于上位数据写入的电压 写入和第二模式使用基于设置信息的电压。 位扫描电路在开始写入之前扫描要写入的存储器单元的数量，并且处理单元将待写入的存储器单元的数量与标准进行比较，并且基于用于写入的第一和第二模式之一确定基于 比较的结果。

公开(公告)号：US07382651B2

公开(公告)日：2008-06-03

申请号：US11616122

申请日：2006-12-26

申请人： Osamu Nagao ,  Yasuyuki Fukuda ,  Hideo Mukai

发明人： Osamu Nagao ,  Yasuyuki Fukuda ,  Hideo Mukai

IPC分类号： G11C16/00

CPC分类号： G11C16/16 ,  G11C16/0483

摘要： In a control order of non-selected blocks at the time of data erase operation of one or a plurality of blocks, the control gate line is controlled to ground potential at first, then subsequently, a transfer transistor of the non-selected blocks is set to be an off-state. Next, high voltage is supplied to the well region and the data of the selected block is erased. Then, the control gate line is charged to the voltage which is used, for instance, at the time of reading out, or to the voltage (Vcg) which is used at the verification (Vcg). After the control gate line is charged to Vcg, the erase voltage supplied to the well region is discharged. Then, the control gate line is returned to ground potential after completing the discharge of the well region, and thus the data erase operation of the block is completed.

摘要翻译： 在一个或多个块的数据擦除操作时以非选择的块的控制顺序，首先将控制栅极线控制为接地电位，然后设置未选择块的传输晶体管 成为一个离开的国家。 接下来，向阱区域提供高电压，并且擦除所选块的数据。 然后，控制栅极线被充电到例如在读出时使用的电压或者在验证时使用的电压（Vcg）（Vcg）。 在控制栅极线被充电到Vcg之后，提供给阱区的擦除电压被放电。 然后，在完成了阱区的放电之后，控制栅极线返回到接地电位，从而完成了块的数据擦除操作。

公开(公告)号：US20070147117A1

公开(公告)日：2007-06-28

申请号：US11616122

申请日：2006-12-26

申请人： Osamu Nagao ,  Yasuyuki Fukuda ,  Hideo Mukai

发明人： Osamu Nagao ,  Yasuyuki Fukuda ,  Hideo Mukai

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/16 ,  G11C16/0483

摘要： In a control order of non-selected blocks at the time of data erase operation of one or a plurality of blocks, the control gate line is controlled to ground potential at first, then subsequently, a transfer transistor of the non-selected blocks is set to be an off-state. Next, high voltage is supplied to the well region and the data of the selected block is erased. Then, the control gate line is charged to the voltage which is used, for instance, at the time of reading out, or to the voltage (Vcg) which is used at the verification (Vcg). After the control gate line is charged to Vcg, the erase voltage supplied to the well region is discharged. Then, the control gate line is returned to ground potential after completing the discharge of the well region, and thus the data erase operation of the block is completed.

摘要翻译： 在一个或多个块的数据擦除操作时以非选择的块的控制顺序，首先将控制栅极线控制为接地电位，然后设置未选择块的传输晶体管 成为一个离开的国家。 接下来，向阱区域提供高电压，并且擦除所选块的数据。 然后，控制栅极线被充电到例如在读出时使用的电压或者在验证时使用的电压（Vcg）（Vcg）。 在控制栅极线被充电到Vcg之后，提供给阱区的擦除电压被放电。 然后，在完成了阱区的放电之后，控制栅极线返回到接地电位，从而完成了块的数据擦除操作。

公开(公告)号：US20100309721A1

公开(公告)日：2010-12-09

申请号：US12793018

申请日：2010-06-03

申请人： Osamu NAGAO

发明人： Osamu NAGAO

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/24

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cells, a bit line, a sense amplifier, a memory circuit and an arithmetic circuit. The memory cells store multiple values in one memory cell. The bit line connected with the memory cells. The sense amplifier supplies a write voltage to the bit line. The memory circuit stores one of write data that is to be written in the memory cell and the number of writes. The arithmetic circuit changes the write data stored in the memory circuit to the number of writes and updates the number of writes. The arithmetic circuit controls the write voltage supplied from the sense amplifier based on the write data, and sets the number of writes in accordance with the write data stored in the memory circuit upon confirmation that each memory cell has reached a predetermined threshold voltage.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储器单元，位线，读出放大器，存储器电路和运算电路。 存储单元将多个值存储在一个存储单元中。 位线与存储单元相连。 读出放大器向位线提供写入电压。 存储电路存储要写入存储单元的写数据和写入数。 算术电路将存储电路中存储的写入数据改变为写入次数，并更新写入次数。 算术电路基于写数据控制从读出放大器提供的写入电压，并且在确认每个存储器单元已经达到预定阈值电压时，根据存储在存储器电路中的写数据来设置写入次数。

公开(公告)号：US20100208519A1

公开(公告)日：2010-08-19

申请号：US12706306

申请日：2010-02-16

申请人： Hitoshi SHIGA ,  Osamu Nagao

发明人： Hitoshi SHIGA ,  Osamu Nagao

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/3404

摘要： First and second data retaining circuits retain data read from memory cell and threshold voltage information indicating where in one of plural threshold voltage distributions threshold voltage of memory cell is located. Calculation device executes calculations among data retained in first and second data retaining circuit and data read by sense amplifier.Control circuit executes first operation of reading data from adjoining memory cell connected to second word line adjoining first word line connected to selected memory cell and retaining the data in first data retaining circuit, and second operation of changing respective word line voltages applied to first word line for reading data or threshold voltage information among plural values and selecting one of plural data read out by the plural values based on data retained in first data retaining circuit. Third operation of externally outputting selected data is executed simultaneously with one of successive first and second operations.

摘要翻译： 第一和第二数据保持电路保持从存储单元读取的数据和指示存储单元的多个阈值电压分布阈值电压位于何处的阈值电压信息。 计算装置执行在第一和第二数据保持电路中保留的数据和由读出放大器读取的数据之间的计算。 控制电路执行从连接到与选择的存储单元连接的第一字线相邻的第二字线的相邻存储单元读取数据并将数据保存在第一数据保持电路中的第一操作，以及改变施加到第一字线的各字线电压的第二操作 用于在多个值之间读取数据或阈值电压信息，并且基于保留在第一数据保持电路中的数据选择由多个值读出的多个数据中的一个。 在连续的第一和第二操作之一中同时执行外部输出所选数据的第三操作。

公开(公告)号：US20100124128A1

公开(公告)日：2010-05-20

申请号：US12556219

申请日：2009-09-09

申请人： Osamu NAGAO ,  Yoshihisa Watanabe ,  Koichi Fukuda

发明人： Osamu NAGAO ,  Yoshihisa Watanabe ,  Koichi Fukuda

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/08 ,  G11C16/16

摘要： A NAND flash memory in which data is erased in blocks, has a plurality of memory cell transistors provided in each of the blocks, the memory cell transistor having a floating gate which is formed via a first gate insulating film on a well formed on a semiconductor substrate and a control gate which is formed on the floating gate via a second gate insulating film, and being capable of rewriting data by controlling an amount of charge accumulated on the floating gate; and a row decoder having a plurality of n-type transfer MOS transistors having drains respectively connected to word lines respectively connected to the control gates of the plurality of memory cell transistors, the row decoder controlling gate voltages and source voltages of the transfer MOS transistors.

摘要翻译： 其中以块为单位擦除数据的NAND闪速存储器具有设置在每个块中的多个存储单元晶体管，存储单元晶体管具有浮置栅极，该浮置栅极通过形成在半导体上的阱上的第一栅极绝缘膜形成 基板和控制栅极，其经由第二栅极绝缘膜形成在浮置栅极上，并且能够通过控制在浮动栅极上累积的电荷量来重写数据; 以及具有多个n型传输MOS晶体管的行解码器，其具有分别连接到分别连接到所述多个存储单元晶体管的控制栅极的字线的漏极，所述行解码器控制所述传输MOS晶体管的栅极电压和源极电压。

公开(公告)号：US20130246730A1

公开(公告)日：2013-09-19

申请号：US13603697

申请日：2012-09-05

申请人： Ayako YAMANO ,  Teruo Takagiwa ,  Koichi Fukuda ,  Hitoshi Shiga ,  Osamu Nagao

发明人： Ayako YAMANO ,  Teruo Takagiwa ,  Koichi Fukuda ,  Hitoshi Shiga ,  Osamu Nagao

IPC分类号： G06F12/08

CPC分类号： G06F12/0891 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C11/5635 ,  G11C16/00 ,  G11C16/16 ,  Y02D10/13

摘要： According to one embodiment, a semiconductor memory device includes a plurality of blocks in a memory cell, each of the blocks acting as an erasure unit of data, the block including a plurality of pages, each of the pages including a plurality of memory cell transistors, each of the memory cell transistors being configured to be an erasure state or a first retention state based on a threshold voltage of the memory cell transistor, and a controller searching data in the block with respect to, writing a first flag denoting effective into a prescribed page of the block with the erasure state, and writing the first flag denoting non-effective into a prescribed page of the block with the first retention state, reading out the prescribed page of the block with the first retention state, and determining that the block is writable when the first flag denotes effective.

摘要翻译： 根据一个实施例，半导体存储器件包括存储器单元中的多个块，每个块用作数据的擦除单元，该块包括多个页，每个页包括多个存储单元晶体管 每个存储单元晶体管被配置为基于存储单元晶体管的阈值电压的擦除状态或第一保持状态，以及控制器搜索块中的数据，将表示有效的第一标志写入到 具有擦除状态的块的规定页面，并且将表示无效的第一标志写入具有第一保持状态的块的规定页面，以第一保留状态读出块的规定页面，并且确定 当第一个标志表示有效时，块是可写的。

公开(公告)号：US20120243330A1

公开(公告)日：2012-09-27

申请号：US13315516

申请日：2011-12-09

申请人： Ayako YAMANO ,  Osamu Nagao ,  Toshiaki Edahiro

发明人： Ayako YAMANO ,  Osamu Nagao ,  Toshiaki Edahiro

IPC分类号： G11C16/14

CPC分类号： G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/3409 ,  G11C16/344

摘要： A nonvolatile semiconductor storage device according to an embodiment includes an erase circuit executing an erase sequence, wherein in the erase sequence, the erase circuit executes: an erase operation to change a selection memory cell group to an erased state, after the erase operation, a soft program operation on the selection memory cell group to solve over-erased state, and after the soft program operation, a first soft program verification operation performed on at least one partial selection memory cell group of a first partial selection memory cell group and a second partial selection memory cell group so as to confirm whether the partial selection memory cell group includes a predetermined number of memory cells or more that have threshold values equal to or more than a predetermined first threshold value, and after the first soft program verification operation.

摘要翻译： 根据实施例的非易失性半导体存储装置包括执行擦除序列的擦除电路，其中在擦除序列中，擦除电路执行：在擦除操作之后将选择存储单元组改变为擦除状态的擦除操作， 对选择存储单元组进行软编程操作以解决过擦除状态，并且在软编程操作之后，对第一部分选择存储单元组和第二部分选择存储单元组的至少一个部分选择存储单元组执行第一软程序验证操作 部分选择存储单元组，以确认部分选择存储单元组是否包括具有等于或大于预定第一阈值的阈值的预定数量的存储单元或更多个，以及在第一软程序验证操作之后。

公开(公告)号：US20120201077A1

公开(公告)日：2012-08-09

申请号：US13234628

申请日：2011-09-16

申请人： Osamu NAGAO

发明人： Osamu NAGAO

IPC分类号： G11C16/10 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5607 ,  G11C11/5614 ,  G11C11/5642 ,  G11C11/5664 ,  G11C11/5671 ,  G11C11/5678 ,  G11C11/5685 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621

摘要： According to one embodiment, a nonvolatile semiconductor memory includes memory cells storing data of multi-level, a bit scan circuit to scan the number of to-be-written memory cells and the number of memory cells that have passed the verify, a processing unit to perform an operation process based on a scan result of the bit scan circuit, and a control circuit to control an operation of writing data according to a first mode in which a voltage used for an upper-data writing is calculated during a lower-data writing and a second mode used a voltage based on setting information. The bit scan circuit scans the number of to-be-written memory cells before starting writing and the processing unit compares the number of to-be-written memory cells with a criterion and determines one of the first and second modes for the writing based on a result of comparison.

摘要翻译： 根据一个实施例，非易失性半导体存储器包括存储多电平数据的存储单元，扫描待写入存储器单元的数量的位扫描电路和通过验证的存储单元的数量;处理单元 基于比特扫描电路的扫描结果执行操作处理，以及控制电路，用于根据第一模式控制写入数据的操作，其中在较低数据期间计算用于上位数据写入的电压 写入和第二模式使用基于设置信息的电压。 位扫描电路在开始写入之前扫描要写入的存储器单元的数量，并且处理单元将待写入的存储器单元的数量与标准进行比较，并且基于用于写入的第一和第二模式之一确定基于 比较的结果。

公开(公告)号：US20100241794A1

公开(公告)日：2010-09-23

申请号：US12725519

申请日：2010-03-17

申请人： Osamu NAGAO ,  Hitoshi Shiga

发明人： Osamu NAGAO ,  Hitoshi Shiga

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7209

摘要： A nonvolatile semiconductor memory device according to one aspect of the present invention includes: a memory cell array provided to perform programming in page units; and a control circuit provided to control the programming. The control circuit includes: means that performs a first detection for memory cells in a part provided as a unit smaller than a page, concurrently with programming to memory cells to be written in a page; and means that subjects the memory cells in the page to a second detection that takes into consideration a failure relief due to a redundant region, when the number of memory cells of unwritten state in the part as detected by the first detection becomes equal to or less than a first constant, and that ends the program operation when the number of memory cells of unwritten state in the page becomes equal to or less than a second constant.

摘要翻译： 根据本发明的一个方面的非易失性半导体存储器件包括：设置为以页为单位执行编程的存储单元阵列; 以及设置用于控制编程的控制电路。 控制电路包括：对存储单元进行第一检测的装置，该存储单元在作为小于页面的单位提供的部分中，同时对要写入页面的存储单元进行编程; 并且意味着当第一检测中检测到的部分中未写入状态的存储单元的数目等于或等于或等于或小于第二检测时，考虑到冗余区域引起的故障缓解， 并且当页面中未写入状态的存储单元的数量等于或小于第二常数时，结束程序操作。