发明申请
- 专利标题： Fast L1 Flush Mechanism
- 专利标题（中）： 快速L1冲洗机构
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申请号： US12785842申请日： 2010-05-24
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公开(公告)号： US20100235670A1公开(公告)日： 2010-09-16
- 发明人: James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
- 申请人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
- 主分类号： G06F1/32
- IPC分类号： G06F1/32
摘要：
In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.
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