- 专利标题: Semiconductor Device and Method of Forming Conductive Pillars in Recessed Region of Peripheral Area Around the Device for Electrical Interconnection to Other Devices
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申请号: US12832821申请日: 2010-07-08
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公开(公告)号: US20100270656A1公开(公告)日: 2010-10-28
- 发明人: Byung Tai Do , Reza A. Pagaila , Linda Pei Ee Chua
- 申请人: Byung Tai Do , Reza A. Pagaila , Linda Pei Ee Chua
- 申请人地址: SG Singapore
- 专利权人: STATS CHIPPAC, LTD.
- 当前专利权人: STATS CHIPPAC, LTD.
- 当前专利权人地址: SG Singapore
- 主分类号: H01L23/544
- IPC分类号: H01L23/544 ; H01L29/06
摘要:
A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside the recessed region and further into the recessed region. A conductive pillar is formed over the first conductive layer within the recessed region. A second insulating layer is formed over the first insulating layer, conductive pillar, and first conductive layer such that the conductive pillar is exposed from the second insulating layer. A dicing channel partially through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the conductive pillar.
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