A power management method for use in a computer system having a processor, a power management module and a phase lock loop circuit (PLL) is provided. The power management module is coupled to a plurality of peripheral modules and the computer system and the processor are capable of being operated in a working state and power saving states. The method includes the following. When the computer system is operated in the working state and the processor is entered into a lowest power consumption state among the power saving states, states of the peripheral modules are detected to determine whether a specific condition has been matched. If the specific condition is matched, the processor is directed to a control state to control the PLL according to a control state configuration.