发明申请
- 专利标题： SUBSTRATE HAVING SINGLE PATTERNED METAL LAYER EXPOSING PATTERNED DIELECTRIC LAYER, CHIP PACKAGE STRUCTURE INCLUDING THE SUBSTRATE, AND MANUFACTURING METHODS THEREOF
- 专利标题（中）： 具有单模式金属层露出图案电介质层的衬底，包括衬底的芯片封装结构及其制造方法
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申请号： US12779800申请日： 2010-05-13
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公开(公告)号： US20100314744A1公开(公告)日： 2010-12-16
- 发明人: Shih-Fu Huang , Yuan-Chang Su , Chia-Cheng Chen , Ta-Chun Lee , Kuang-Hsiung Chen
- 申请人： Shih-Fu Huang , Yuan-Chang Su , Chia-Cheng Chen , Ta-Chun Lee , Kuang-Hsiung Chen
- 优先权： TW98126172 20090804
- 主分类号： H01L23/498
- IPC分类号： H01L23/498 ; H01L21/768
摘要：
A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die.
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