公开(公告)号：US08569894B2

公开(公告)日：2013-10-29

申请号：US13006340

申请日：2011-01-13

Applicant: Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

Inventor： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/14 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/49155 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.

Abstract translation: 半导体封装包括基板单元，与第一接触焊盘电连接的管芯，以及覆盖第一图案化导电层和管芯的封装体。 基板单元包括：（1）第一图案化导电层; （2）暴露第一图案化导电层的一部分以形成第一接触焊盘的第一电介质层; （3）第二图案化导电层; （4）限定从第一图案化导电层延伸到第二图案化导电层的开口的第二介电层，其中第二图案化导电层包括由第二介电层暴露的第二接触焊盘; 和（5）通过开口从第一图案化导电层延伸到第二接触垫的导电柱，每个导电柱填充相应的一个开口。 导电柱中的至少一个限定了空腔。

公开(公告)号：US20110057301A1

公开(公告)日：2011-03-10

申请号：US12607405

申请日：2009-10-28

Applicant: Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt

Inventor： Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt

IPC: H01L23/488

CPC classification number: H01L23/49816 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/28 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.

Abstract translation: 半导体封装包括图案化金属箔，芯片，电线，图案化电介质层，粘合剂层和模塑料。 图案化金属箔具有与其相对的第一表面和第二表面。 图案化的电介质层设置在第二表面上并且具有暴露图案化金属箔的至少一部分的开口以形成用于外部电连接的接头。 芯片设置在第一表面上。 粘合剂层设置在芯片和图案化的金属箔之间。 导线分别连接芯片和图案化金属箔。 图案化电介质层位于电线和图案化金属箔之间的交叉点下方。 图案化电介质层，导线和图案化金属箔在平面上彼此重叠。 模塑料配置在第一表面上并覆盖芯片和电线。

公开(公告)号：US20100289132A1

公开(公告)日：2010-11-18

申请号：US12716873

申请日：2010-03-03

Applicant: Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Chia-Ching Chen

Inventor： Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Chia-Ching Chen

IPC: H01L23/48 ,  H05K1/03 ,  H05K3/10

CPC classification number: H05K3/20 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/28 ,  H05K2203/0152 ,  H05K2203/1536 ,  H05K2203/1563 ,  Y10T29/49155 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A substrate having single patterned metal layer applied in a package is provided. The substrate includes a first patterned dielectric layer, a patterned metal layer and a second patterned dielectric layer, wherein the patterned metal layer is embedded in the first patterned dielectric layer. Also, the top surfaces of the patterned metal layer and the first patterned dielectric layer lie in the same plane. At least part of the patterned metal layer are exposed from the holes formed on the lower surface of the first patterned dielectric layer, so as to form plural first contact pads for electrical connection downwardly. The second patterned dielectric layer, formed above the patterned metal layer and the first patterned dielectric layer, at least exposes part of the patterned metal layer to form plural second contact pads at the top surface of the patterned metal layer for electrical connection upwardly.

Abstract translation: 提供了一种施加在封装中的具有单一图案化金属层的衬底。 衬底包括第一图案化电介质层，图案化金属层和第二图案化电介质层，其中图案化金属层嵌入第一图案化电介质层中。 此外，图案化金属层和第一图案化电介质层的顶表面位于相同的平面中。 图案化金属层的至少一部分从形成在第一图案化电介质层的下表面上的孔露出，从而形成用于向下电连接的多个第一接触焊盘。 形成在图案化金属层和第一图案化电介质层之上的第二图案化电介质层至少暴露图案化金属层的一部分以在图案化金属层的顶表面处形成多个第二接触焊盘，用于向上电连接。

公开(公告)号：US08284561B2

公开(公告)日：2012-10-09

申请号：US12850872

申请日：2010-08-05

Applicant: Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt ,  Ming-Chiang Lee

Inventor： Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt ,  Ming-Chiang Lee

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/186 ,  H01L2224/16225 ,  H01L2924/15153 ,  H01L2924/15321 ,  H05K3/0097 ,  H05K3/4697 ,  H05K2201/0352 ,  H05K2203/1536 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time.

Abstract translation: 本发明通过提供预制的层压结构，连接或堆叠预成型的层压结构并将至少一个电子部件安装到接合的结构来指导嵌入式组件封装结构的制造方法。 通过制造方法，可以以较低的循环时间大大提高生产产量。

公开(公告)号：US20120033394A1

公开(公告)日：2012-02-09

申请号：US12850872

申请日：2010-08-05

Applicant: Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt ,  Ming-Chiang Lee

Inventor： Yuan-Chang Su ,  Shih-Fu Huang ,  Bernd Karl Appelt ,  Ming-Chiang Lee

IPC: H05K7/10 ,  H05K3/42 ,  H05K3/30

CPC classification number: H05K1/186 ,  H01L2224/16225 ,  H01L2924/15153 ,  H01L2924/15321 ,  H05K3/0097 ,  H05K3/4697 ,  H05K2201/0352 ,  H05K2203/1536 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time.

Abstract translation: 本发明通过提供预制的层压结构，连接或堆叠预成型的层压结构并将至少一个电子部件安装到接合的结构来指导嵌入式组件封装结构的制造方法。 通过制造方法，可以以较低的循环时间大大提高生产产量。

公开(公告)号：US20110194265A1

公开(公告)日：2011-08-11

申请号：US12701486

申请日：2010-02-05

Applicant: Yuan-Chang Su ,  Shih-Fu Huang ,  Ming-Chiang Lee ,  Chien-Hao Wang

Inventor： Yuan-Chang Su ,  Shih-Fu Huang ,  Ming-Chiang Lee ,  Chien-Hao Wang

IPC: H05K1/18 ,  H05K3/46 ,  H05K3/40

CPC classification number: H01L23/5389 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embodiment of an embedded component substrate includes: (1) a semiconductor device including lower, lateral, and upper surfaces; (2) a first patterned conductive layer including a first electrical interconnect extending substantially laterally within the first patterned conductive layer; (3) a second electrical interconnect extending substantially vertically from a first surface of the first interconnect, and including lateral and upper surfaces, and a lower surface adjacent to the first surface; (4) a dielectric layer including an opening extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer, where: (a) the dielectric layer substantially covers the lateral and upper surfaces of the device, and at least a portion of the lateral surface of the second interconnect; and (b) the second interconnect substantially fills the opening; and (5) a second patterned conductive layer adjacent to the upper surfaces of the dielectric layer and the second interconnect.

Abstract translation: 嵌入式部件基板的一个实施例包括：（1）包括下表面，外表面和上表面的半导体器件; （2）第一图案化导电层，包括在第一图案化导电层内基本横向延伸的第一电互连; （3）从所述第一互连的第一表面大致垂直延伸并且包括侧表面和上表面以及与所述第一表面相邻的下表面延伸的第二电互连; （4）介电层，包括从电介质层的上表面延伸到电介质层的下表面的开口，其中：（a）电介质层基本上覆盖器件的横向和上表面，并且至少一个 第二互连的侧表面的部分; 和（b）第二互连基本上填充开口; 和（5）与电介质层和第二互连件的上表面相邻的第二图案化导电层。

公开(公告)号：US08357861B2

公开(公告)日：2013-01-22

申请号：US12694539

申请日：2010-01-27

Applicant: Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Hsiung Hsieh

Inventor： Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Hsiung Hsieh

IPC: H05K1/11

CPC classification number: H05K3/403 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/027 ,  H05K3/427 ,  H05K2201/09645 ,  H05K2203/107 ,  H01L2924/00

Abstract: A circuit board, a chip package structure and a fabrication method of the circuit board are provided. By applying the fabrication method, a plurality of conductive channels can be formed in a single through hole of the circuit substrate. Unlike the conductive channels respectively formed in the through holes according to the related art, the conductive channels of the proposed circuit board can be formed in a single through hole. As such, it is conducive to the expansion of available layout area of the circuit board, the increase in layout flexibility, and the improvement of layout density of the circuit board.

Abstract translation: 提供电路板，芯片封装结构和电路板的制造方法。 通过应用制造方法，可以在电路基板的单个通孔中形成多个导电沟道。 与根据现有技术的通孔中分别形成的导电通道不同，所提出的电路板的导电通道可以形成在单个通孔中。 因此，有利于电路板可用布局面积的扩大，布局灵活性的提高以及电路板布局密度的提高。

公开(公告)号：US08320134B2

公开(公告)日：2012-11-27

申请号：US12701486

申请日：2010-02-05

Applicant: Yuan-Chang Su ,  Shih-Fu Huang ,  Ming-Chiang Lee ,  Chien-Hao Wang

Inventor： Yuan-Chang Su ,  Shih-Fu Huang ,  Ming-Chiang Lee ,  Chien-Hao Wang

IPC: H05K1/18

CPC classification number: H01L23/5389 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embodiment of an embedded component substrate includes: (1) a semiconductor device including lower, lateral, and upper surfaces; (2) a first patterned conductive layer including a first electrical interconnect extending substantially laterally within the first patterned conductive layer; (3) a second electrical interconnect extending substantially vertically from a first surface of the first interconnect, and including lateral and upper surfaces, and a lower surface adjacent to the first surface; (4) a dielectric layer including an opening extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer, where: (a) the dielectric layer substantially covers the lateral and upper surfaces of the device, and at least a portion of the lateral surface of the second interconnect; and (b) the second interconnect substantially fills the opening; and (5) a second patterned conductive layer adjacent to the upper surfaces of the dielectric layer and the second interconnect.

Abstract translation: 嵌入式部件基板的一个实施例包括：（1）包括下表面，外表面和上表面的半导体器件; （2）第一图案化导电层，包括在第一图案化导电层内基本横向延伸的第一电互连; （3）从所述第一互连的第一表面大致垂直延伸并且包括侧表面和上表面以及与所述第一表面相邻的下表面延伸的第二电互连; （4）介电层，包括从电介质层的上表面延伸到电介质层的下表面的开口，其中：（a）电介质层基本上覆盖器件的横向和上表面，并且至少一个 第二互连的侧表面的部分; 和（b）第二互连基本上填充开口; 和（5）与电介质层和第二互连件的上表面相邻的第二图案化导电层。

公开(公告)号：US20120153493A1

公开(公告)日：2012-06-21

申请号：US12972046

申请日：2010-12-17

Applicant: CHUN-CHE LEE ,  YUAN-CHANG SU ,  MING CHIANG LEE ,  SHIH-FU HUANG

Inventor： CHUN-CHE LEE ,  YUAN-CHANG SU ,  MING CHIANG LEE ,  SHIH-FU HUANG

IPC: H01L23/48 ,  H01L21/28

CPC classification number: H01L25/16 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: An embedded component device includes an electronic component including an electrical contact, an upper patterned conductive layer, a dielectric layer between the upper patterned conductive layer and the electronic component, a first electrical interconnect, a lower patterned conductive layer, a conductive via, and a second electrical interconnect. The dielectric layer has a first opening exposing the electrical contact, and a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer. The first electrical interconnect extends from the electrical contact to the upper patterned conductive layer, and fills the first opening. The second opening has an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer. The conductive via is located at the lower portion of the second opening. The second electrical interconnect fills the upper portion of the second opening.

Abstract translation: 嵌入式组件装置包括电子部件，其包括电接触，上图案化导电层，上图案化导电层和电子部件之间的介电层，第一电互连，下图案化导电层，导电通孔和 第二电互连。 电介质层具有暴露电接触的第一开口和从下图案化导电层延伸到上图案化导电层的第二开口。 第一电互连从电接触延伸到上图案化导电层，并填充第一开口。 第二开口具有暴露上部图案化导电层的上部和暴露下部图案化导电层的下部。 导电通孔位于第二开口的下部。 第二电互连填充第二开口的上部。

公开(公告)号：US20110169150A1

公开(公告)日：2011-07-14

申请号：US13006340

申请日：2011-01-13

Applicant: Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

Inventor： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

IPC: H01L23/495 ,  H01L21/60 ,  H05K3/10

CPC classification number: H01L24/14 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/49155 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.

Abstract translation: 半导体封装包括基板单元，与第一接触焊盘电连接的管芯，以及覆盖第一图案化导电层和管芯的封装体。 基板单元包括：（1）第一图案化导电层; （2）暴露第一图案化导电层的一部分以形成第一接触焊盘的第一电介质层; （3）第二图案化导电层; （4）限定从第一图案化导电层延伸到第二图案化导电层的开口的第二介电层，其中第二图案化导电层包括由第二介电层暴露的第二接触焊盘; 和（5）通过开口从第一图案化导电层延伸到第二接触垫的导电柱，每个导电柱填充相应的一个开口。 导电柱中的至少一个限定了空腔。