发明申请
US20100320596A1 METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE USING THE SAME
有权
用于制造半导体封装的方法和使用该半导体封装的半导体封装
- 专利标题: METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE USING THE SAME
- 专利标题(中): 用于制造半导体封装的方法和使用该半导体封装的半导体封装
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申请号: US12565171申请日: 2009-09-23
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公开(公告)号: US20100320596A1公开(公告)日: 2010-12-23
- 发明人: Yong Sung Eom , Kwang-Seong Choi , Hyun-Cheol Bae , Jong-Hyun Lee , Jong Tae Moon
- 申请人: Yong Sung Eom , Kwang-Seong Choi , Hyun-Cheol Bae , Jong-Hyun Lee , Jong Tae Moon
- 申请人地址: KR Daejeon
- 专利权人: ELECTRONICS AND TELECOMMUNICATION RESEARCH INSTITUTE
- 当前专利权人: ELECTRONICS AND TELECOMMUNICATION RESEARCH INSTITUTE
- 当前专利权人地址: KR Daejeon
- 优先权: KR10-2009-0055478 20090622
- 主分类号: H01L23/488
- IPC分类号: H01L23/488 ; H01L21/60
摘要:
Provided is a method for fabricating semiconductor package and a semiconductor package fabricated using the same. The method for fabricating semiconductor package dopes a mixture including the polymer material and the solder particle on the substrate in which the terminal is formed and applies heat, and thus the solder particle flows (or diffuses) toward the terminal in the heated polymer resin to adhere to the exposed surface of the terminal, i.e., the side surface and upper surface of the terminal, thereby forming the solder layer. The solder layer improves the adhesive strength between the terminal of the semiconductor chip and the terminal of the substrate in the subsequent flip chip bonding process.
公开/授权文献
- US08030200B2 Method for fabricating a semiconductor package 公开/授权日:2011-10-04
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