发明申请
US20100330707A1 Robust Self-Aligned Process for Sub-65nm Current-Perpendicular Junction Pillars
有权
用于子65nm电流 - 垂直接合柱的稳健自对准过程
- 专利标题： Robust Self-Aligned Process for Sub-65nm Current-Perpendicular Junction Pillars
- 专利标题（中）： 用于子65nm电流 - 垂直接合柱的稳健自对准过程
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申请号： US11627824申请日： 2007-01-26
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公开(公告)号： US20100330707A1公开(公告)日： 2010-12-30
- 发明人: Xin Jiang , Stuart Stephen Papworth Parkin , Jonathan Sun
- 申请人： Xin Jiang , Stuart Stephen Papworth Parkin , Jonathan Sun
- 主分类号： H01L43/12
- IPC分类号： H01L43/12 ; C23F4/00
摘要：
A method for fabricating a device includes forming a first insulation layer to cover a removable mask and a device structure that has been defined by the mask. The device structure is below the mask. The mask is lifted off to expose a top portion of the device structure. A conductive island structure is formed over the first insulation layer and the exposed top portion of the device structure. The first insulation layer and the conductive island structure are covered with a second insulation layer. A contact is formed through the second insulation layer to the conductive island structure.